From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 76ADF266B67; Mon, 28 Apr 2025 12:44:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745844291; cv=none; b=svVmoj4izGUr+sQ0CxUz0yIhx0qFXGOn/ktpzOM9WxQwaIb6VMEgUEbCqw/klfKcbXrUMDS4msrOjENlWSqNHpQvllZzbLTGHz1zb8YfRAMxuMKZq0i0q2Ve4vnwKnZR6t2OtS8gYEttoIdLZpN1uWHHlxz5ZS/qKmMaVZBzTqw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745844291; c=relaxed/simple; bh=69u4x2iVX3CML3z65mNSFOpfvvJMY1UtVIYXajlF58c=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BSinGpThjptCgUMGjc9VGvf2q3u/HgMHfY6kkTXIQbnX7GtN7qwcxCQpeh71bT2rGqsIDnJRMFnqAGFw9C/h8Ce8PHkIr4MxpZhzGMWKVyFfiynVWkMP5Pe35pvtWTfBo3jrUM1OB5KWsK7ugbogz9dB6btQmdp1ISFYAFzXQaI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4285E1516; Mon, 28 Apr 2025 05:44:41 -0700 (PDT) Received: from donnerap.manchester.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3B9463F66E; Mon, 28 Apr 2025 05:44:45 -0700 (PDT) Date: Mon, 28 Apr 2025 13:44:35 +0100 From: Andre Przywara To: Yixun Lan , Krzysztof Kozlowski Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Corentin Labbe , , , , , Subject: Re: [PATCH v2 1/5] dt-bindings: sram: sunxi-sram: Add A523 compatible Message-ID: <20250428134435.76e19d29@donnerap.manchester.arm.com> In-Reply-To: <20250428122156-GYA56330@gentoo> References: <20250424-01-sun55i-emac0-v2-0-833f04d23e1d@gentoo.org> <20250424-01-sun55i-emac0-v2-1-833f04d23e1d@gentoo.org> <20250428-vegan-stoic-flamingo-1d1a2a@kuoka> <20250428122156-GYA56330@gentoo> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Mon, 28 Apr 2025 12:21:56 +0000 Yixun Lan wrote: > Hi Krzysztof, >=20 > On 09:21 Mon 28 Apr , Krzysztof Kozlowski wrote: > > On Thu, Apr 24, 2025 at 06:08:39PM GMT, Yixun Lan wrote: =20 > > > The Allwinner A523 family of SoCs have their "system control" registe= rs > > > compatible to the A64 SoC, so add the new SoC specific compatible str= ing. > > >=20 > > > Reviewed-by: Andre Przywara > > > Signed-off-by: Yixun Lan > > > --- > > > .../devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml= | 1 + > > > 1 file changed, 1 insertion(+) > > >=20 > > > diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a= 10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,s= un4i-a10-system-control.yaml > > > index a7236f7db4ec34d44c4e2268f76281ef8ed83189..e7f7cf72719ea884d48ff= f69620467ff2834913b 100644 > > > --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-syst= em-control.yaml > > > +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-syst= em-control.yaml > > > @@ -50,6 +50,7 @@ properties: > > > - enum: > > > - allwinner,sun50i-a100-system-control > > > - allwinner,sun50i-h6-system-control > > > + - allwinner,sun55i-a523-system-control > > > - const: allwinner,sun50i-a64-system-control =20 > >=20 > > No update for the children (sram)? > > =20 > No, I don't think there is sub node for sram > From address map of A527, there is total 4KB size space of > this section which unlikely has sram available. That's something else, though. This system controller here *also* contains a register to switch access to SRAM blocks between the CPU and the devices. The actual SRAM blocks are somewhere else (hence the empty ranges; property), check the H616 for instance: syscon: syscon@3000000 { compatible =3D "allwinner,sun50i-h616-system-control"; reg =3D <0x03000000 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; ranges; sram_c: sram@28000 { compatible =3D "mmio-sram"; reg =3D <0x00028000 0x30000>; Krzysztof, we haven't worked out the SRAM regions yet, we typically add them only when we need them. I think the display engine is a prominent user, and support for that is quite a bit out at the moment. =46rom a compatibility standpoint it should be fine to leave this empty for now, if I am not mistaken? Cheers, Andre > but I do see some BROM/SRAM space from 0x0000 0000 - 0x0006 3FFF .. > (which should not be relavant to this patch series..) >=20