From: Jacob Keller <jacob.e.keller@intel.com>
To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>,
Anthony Nguyen <anthony.l.nguyen@intel.com>,
netdev <netdev@vger.kernel.org>
Cc: Jacob Keller <jacob.e.keller@intel.com>,
Michal Kubiak <michal.kubiak@intel.com>,
Aleksandr Loktionov <aleksandr.loktionov@intel.com>,
Karol Kolacinski <karol.kolacinski@intel.com>,
Przemek Kitszel <przemyslaw.kitszel@intel.com>,
Milena Olech <milena.olech@intel.com>,
Paul Menzel <pmenzel@molgen.mpg.de>
Subject: [PATCH v4 06/15] ice: add TSPLL log config helper
Date: Thu, 01 May 2025 15:54:17 -0700 [thread overview]
Message-ID: <20250501-kk-tspll-improvements-alignment-v4-6-24c83d0ce7a8@intel.com> (raw)
In-Reply-To: <20250501-kk-tspll-improvements-alignment-v4-0-24c83d0ce7a8@intel.com>
From: Karol Kolacinski <karol.kolacinski@intel.com>
Add a helper function to print new/current TSPLL config. This helps
avoid unnecessary casts from u8 to enums.
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_tspll.c | 54 +++++++++++++++++-------------
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ethernet/intel/ice/ice_tspll.c
index cf0e37296796c5bbda011d027dc8ef007b0e2021..08af4ced50eb877dce5944d87a90d0dcdb49ff2e 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -89,6 +89,26 @@ static const char *ice_tspll_clk_src_str(enum ice_clk_src clk_src)
}
}
+/**
+ * ice_tspll_log_cfg - Log current/new TSPLL configuration
+ * @hw: Pointer to the HW struct
+ * @enable: CGU enabled/disabled
+ * @clk_src: Current clock source
+ * @tspll_freq: Current clock frequency
+ * @lock: CGU lock status
+ * @new_cfg: true if this is a new config
+ */
+static void ice_tspll_log_cfg(struct ice_hw *hw, bool enable, u8 clk_src,
+ u8 tspll_freq, bool lock, bool new_cfg)
+{
+ dev_dbg(ice_hw_to_dev(hw),
+ "%s TSPLL configuration -- %s, src %s, freq %s, PLL %s\n",
+ new_cfg ? "New" : "Current", str_enabled_disabled(enable),
+ ice_tspll_clk_src_str((enum ice_clk_src)clk_src),
+ ice_tspll_clk_freq_str((enum ice_tspll_freq)tspll_freq),
+ lock ? "locked" : "unlocked");
+}
+
/**
* ice_tspll_cfg_e82x - Configure the Clock Generation Unit TSPLL
* @hw: Pointer to the HW struct
@@ -144,12 +164,9 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
- /* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "Current TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw24.ts_pll_enable),
- ice_tspll_clk_src_str(dw24.time_ref_sel),
- ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
- bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
+ ice_tspll_log_cfg(hw, dw24.ts_pll_enable, dw24.time_ref_sel,
+ dw9.time_ref_freq_sel, bwm_lf.plllock_true_lock_cri,
+ false);
/* Disable the PLL before changing the clock source or frequency */
if (dw24.ts_pll_enable) {
@@ -222,12 +239,8 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EBUSY;
}
- /* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "New TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw24.ts_pll_enable),
- ice_tspll_clk_src_str(dw24.time_ref_sel),
- ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
- bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
+ ice_tspll_log_cfg(hw, dw24.ts_pll_enable, clk_src, clk_freq, true,
+ true);
return 0;
}
@@ -316,12 +329,9 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
- /* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "Current TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw23.ts_pll_enable),
- ice_tspll_clk_src_str(dw23.time_ref_sel),
- ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
- ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
+ ice_tspll_log_cfg(hw, dw23.ts_pll_enable, dw23.time_ref_sel,
+ dw9.time_ref_freq_sel,
+ ro_lock.plllock_true_lock_cri, false);
/* Disable the PLL before changing the clock source or frequency */
if (dw23.ts_pll_enable) {
@@ -414,12 +424,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EBUSY;
}
- /* Log the current clock configuration */
- ice_debug(hw, ICE_DBG_PTP, "New TSPLL configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
- str_enabled_disabled(dw23.ts_pll_enable),
- ice_tspll_clk_src_str(dw23.time_ref_sel),
- ice_tspll_clk_freq_str(dw9.time_ref_freq_sel),
- ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
+ ice_tspll_log_cfg(hw, dw23.ts_pll_enable, clk_src, clk_freq, true,
+ true);
return 0;
}
--
2.48.1.397.gec9d649cc640
next prev parent reply other threads:[~2025-05-01 22:54 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-01 22:54 [PATCH v4 00/15] ice: Separate TSPLL from PTP and clean up Jacob Keller
2025-05-01 22:54 ` [PATCH v4 01/15] ice: move TSPLL functions to a separate file Jacob Keller
2025-05-22 14:13 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 02/15] ice: rename TSPLL and CGU functions and definitions Jacob Keller
2025-05-22 14:15 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 03/15] ice: fix E825-C TSPLL register definitions Jacob Keller
2025-05-22 14:18 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 04/15] ice: remove ice_tspll_params_e825 definitions Jacob Keller
2025-05-22 14:19 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 05/15] ice: use designated initializers for TSPLL consts Jacob Keller
2025-05-22 14:21 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` Jacob Keller [this message]
2025-05-22 14:23 ` [Intel-wired-lan] [PATCH v4 06/15] ice: add TSPLL log config helper Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 07/15] ice: add ICE_READ/WRITE_CGU_REG_OR_DIE helpers Jacob Keller
2025-05-22 14:24 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 08/15] ice: clear time_sync_en field for E825-C during reprogramming Jacob Keller
2025-05-22 14:27 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 09/15] ice: read TSPLL registers again before reporting status Jacob Keller
2025-05-22 14:28 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 10/15] ice: use bitfields instead of unions for CGU regs Jacob Keller
2025-05-22 14:30 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 11/15] ice: add multiple TSPLL helpers Jacob Keller
2025-05-22 14:32 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 12/15] ice: wait before enabling TSPLL Jacob Keller
2025-05-22 14:34 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 13/15] ice: fall back to TCXO on TSPLL lock fail Jacob Keller
2025-05-22 14:36 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 14/15] ice: move TSPLL init calls to ice_ptp.c Jacob Keller
2025-05-22 14:38 ` [Intel-wired-lan] " Rinitha, SX
2025-05-01 22:54 ` [PATCH v4 15/15] ice: default to TIME_REF instead of TXCO on E825-C Jacob Keller
2025-05-22 14:40 ` [Intel-wired-lan] " Rinitha, SX
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