From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mxout1.routing.net (mxout1.routing.net [134.0.28.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2218B27A129; Fri, 16 May 2025 18:02:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.0.28.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747418529; cv=none; b=WmESr7mlUXFtDwgTSc0XWJdWKhY/m/Sj9e5lwxMaWkCeDUTOYwqIH7odZNCJ/K0d1NQbgHKTwqG8WDFAz++RsAPdDnAA6/4qltKP2Erz2hhuBcXAmnOAPwLZBS/g5UadLM+i6vvjbWETk8QHMpW8CQaCvNIZvxvPqFs143rqTHQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747418529; c=relaxed/simple; bh=MXoHdJdXDAaIgTdoPAI3IjgNKGscDJ3hK37VxvEd/pw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=llpKvhv/ZDvgmzxwTnKr5m00mSkXG16b6UBC+2yA9sRZ3H4vFvkSzeWqNY7tvPgXhW+qmI0ggsLYwFaOhCg3yfHCpicgDMhaXnhwJxk+9PHlJZTCVEKWMC7/t/tINdc7dGWPDk89pgQBLUbukPG3spjleDpjwb1bZpTjZlJ0vdA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de; spf=pass smtp.mailfrom=fw-web.de; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b=xUNjATwf; arc=none smtp.client-ip=134.0.28.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fw-web.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b="xUNjATwf" Received: from mxbulk.masterlogin.de (unknown [192.168.10.85]) by mxout1.routing.net (Postfix) with ESMTP id C297640567; Fri, 16 May 2025 18:01:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1747418518; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Zletv3U5pRRedodS7LIwp9KMfAgSeQxiaCAd7v3PwI0=; b=xUNjATwfXxQ+qJen1H8Ii5NK65OgoQdL4fjCNIbyt0mT2wqLueLBy9vANq6JclDyIibDge f7Yu/FJkWRlXOmF9AhMMTaxusDioI4iyd1Jc6Br8kIluGRsjZ+3ZL23exWvVB07EiQCC0r 4ST76dL79DiXEA4i3abH5tA6Ib4N8Yo= Received: from frank-u24.. (fttx-pool-157.180.226.139.bambit.de [157.180.226.139]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id 76DBA1226C1; Fri, 16 May 2025 18:01:57 +0000 (UTC) From: Frank Wunderlich To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Landen Chao , DENG Qingfang , Sean Wang , Daniel Golle , Lorenzo Bianconi , Felix Fietkau , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 07/14] arm64: dts: mediatek: mt7988: add phy calibration efuse subnodes Date: Fri, 16 May 2025 20:01:38 +0200 Message-ID: <20250516180147.10416-9-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250516180147.10416-1-linux@fw-web.de> References: <20250516180147.10416-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Frank Wunderlich MT7988 contains buildin mt753x switch which needs calibration data from efuse. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 64466acb0e71..029699e4eb02 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -696,6 +696,22 @@ efuse@11f50000 { lvts_calibration: calib@918 { reg = <0x918 0x28>; }; + + phy_calibration_p0: calib@940 { + reg = <0x940 0x10>; + }; + + phy_calibration_p1: calib@954 { + reg = <0x954 0x10>; + }; + + phy_calibration_p2: calib@968 { + reg = <0x968 0x10>; + }; + + phy_calibration_p3: calib@97c { + reg = <0x97c 0x10>; + }; }; clock-controller@15000000 { -- 2.43.0