From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B69DD21C161; Tue, 20 May 2025 20:59:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747774774; cv=none; b=ETH8T5hXh+GOKOLU1QaWd2KqRxbCHMzkeOHWvsZwP8/OQg9tpxy/PE6DvK2XuYk0kc/ccExB2le8ZJnTSBLQPqXjbH/TEzkmeLwfYsiK6Zmt2cX9e9BL1yyLpx+NKEyqzH3wcwXllx3XJmuqPBAf/PdqSfKT1gozWYXhPRiUlgo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747774774; c=relaxed/simple; bh=DGZ9lUK0UD2U2MKLNMEgme8ThpJu7wwac3m3/+tfgEw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BvOSDHi5/9K7k62z2dBNm3W8oItaDR4aLZl6Ive20X7Xrz3SxSh5EkI52ib96F7vvPl89PUkQHhW9396Z5h/UJNwE+2eOG+vSqbNCRIbTAYS1+kw7ACmvDUVX8gvBhxCBpo/NQxp2IPlX1k0porIXGtX8EYJ3GkQ9pAUJ8kmo8E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=aZFIxMH7; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="aZFIxMH7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747774772; x=1779310772; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DGZ9lUK0UD2U2MKLNMEgme8ThpJu7wwac3m3/+tfgEw=; b=aZFIxMH7VQ563VAII3Xu5uFPJDRqwTrCCxg/nodUzlmx0XMVErGlfE2H MYMekL4avMVRxRAgbiXatQ81Daa9+EMZFJrB8qNMBEgcPbGmnxqlECICZ u33cbMt3tr7Kky/mBy2SADxPp9iv4DGgPfX03gPtIDePTBW9GAwi/SPM5 yVt/rDhmD4EJkt6YqDeLlmXPVlNHjcv7VTyPH3US7VSIldfnO+vzGjdCn obp8Z249URtQcuL1tclcEFD/ivnbuW8ZfKi/FqZUtO4xHUyl+1hJtddC6 6oeKrXcA88xYPvsTxJBpHOSb+yU4NOygac1iSvk3hlG4qhcIzNr+5Di1a g==; X-CSE-ConnectionGUID: DdsdprD3QHeqVbKiaRJzCA== X-CSE-MsgGUID: YLZFUWiiREKF+BFiFCIcnw== X-IronPort-AV: E=McAfee;i="6700,10204,11439"; a="67142688" X-IronPort-AV: E=Sophos;i="6.15,302,1739865600"; d="scan'208";a="67142688" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2025 13:59:31 -0700 X-CSE-ConnectionGUID: 8+vvk6ItTUiONbZfb+/wcQ== X-CSE-MsgGUID: y05lLWIVRFKrczPRE0bWOw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,302,1739865600"; d="scan'208";a="139850863" Received: from anguy11-upstream.jf.intel.com ([10.166.9.133]) by fmviesa007.fm.intel.com with ESMTP; 20 May 2025 13:59:30 -0700 From: Tony Nguyen To: davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, edumazet@google.com, andrew+netdev@lunn.ch, netdev@vger.kernel.org Cc: Alexander Lobakin , anthony.l.nguyen@intel.com, maciej.fijalkowski@intel.com, magnus.karlsson@intel.com, michal.kubiak@intel.com, przemyslaw.kitszel@intel.com, ast@kernel.org, daniel@iogearbox.net, hawk@kernel.org, john.fastabend@gmail.com, horms@kernel.org, bpf@vger.kernel.org Subject: [PATCH net-next 02/16] libeth: support native XDP and register memory model Date: Tue, 20 May 2025 13:59:03 -0700 Message-ID: <20250520205920.2134829-3-anthony.l.nguyen@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250520205920.2134829-1-anthony.l.nguyen@intel.com> References: <20250520205920.2134829-1-anthony.l.nguyen@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Alexander Lobakin Expand libeth's Page Pool functionality by adding native XDP support. This means picking the appropriate headroom and DMA direction. Also, register all the created &page_pools as XDP memory models. A driver then can call xdp_rxq_info_attach_page_pool() when registering its RxQ info. Signed-off-by: Alexander Lobakin Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/libeth/rx.c | 20 +++++++++++++++----- include/net/libeth/rx.h | 6 +++++- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/intel/libeth/rx.c b/drivers/net/ethernet/intel/libeth/rx.c index aa5d878181f7..c0be9cb043a1 100644 --- a/drivers/net/ethernet/intel/libeth/rx.c +++ b/drivers/net/ethernet/intel/libeth/rx.c @@ -70,7 +70,7 @@ static u32 libeth_rx_hw_len_truesize(const struct page_pool_params *pp, static bool libeth_rx_page_pool_params(struct libeth_fq *fq, struct page_pool_params *pp) { - pp->offset = LIBETH_SKB_HEADROOM; + pp->offset = fq->xdp ? LIBETH_XDP_HEADROOM : LIBETH_SKB_HEADROOM; /* HW-writeable / syncable length per one page */ pp->max_len = LIBETH_RX_PAGE_LEN(pp->offset); @@ -157,11 +157,12 @@ int libeth_rx_fq_create(struct libeth_fq *fq, struct napi_struct *napi) .dev = napi->dev->dev.parent, .netdev = napi->dev, .napi = napi, - .dma_dir = DMA_FROM_DEVICE, }; struct libeth_fqe *fqes; struct page_pool *pool; - bool ret; + int ret; + + pp.dma_dir = fq->xdp ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; if (!fq->hsplit) ret = libeth_rx_page_pool_params(fq, &pp); @@ -175,18 +176,26 @@ int libeth_rx_fq_create(struct libeth_fq *fq, struct napi_struct *napi) return PTR_ERR(pool); fqes = kvcalloc_node(fq->count, sizeof(*fqes), GFP_KERNEL, fq->nid); - if (!fqes) + if (!fqes) { + ret = -ENOMEM; goto err_buf; + } + + ret = xdp_reg_page_pool(pool); + if (ret) + goto err_mem; fq->fqes = fqes; fq->pp = pool; return 0; +err_mem: + kvfree(fqes); err_buf: page_pool_destroy(pool); - return -ENOMEM; + return ret; } EXPORT_SYMBOL_GPL(libeth_rx_fq_create); @@ -196,6 +205,7 @@ EXPORT_SYMBOL_GPL(libeth_rx_fq_create); */ void libeth_rx_fq_destroy(struct libeth_fq *fq) { + xdp_unreg_page_pool(fq->pp); kvfree(fq->fqes); page_pool_destroy(fq->pp); } diff --git a/include/net/libeth/rx.h b/include/net/libeth/rx.h index 7d5dc58984b1..5d991404845e 100644 --- a/include/net/libeth/rx.h +++ b/include/net/libeth/rx.h @@ -13,8 +13,10 @@ /* Space reserved in front of each frame */ #define LIBETH_SKB_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN) +#define LIBETH_XDP_HEADROOM (ALIGN(XDP_PACKET_HEADROOM, NET_SKB_PAD) + \ + NET_IP_ALIGN) /* Maximum headroom for worst-case calculations */ -#define LIBETH_MAX_HEADROOM LIBETH_SKB_HEADROOM +#define LIBETH_MAX_HEADROOM LIBETH_XDP_HEADROOM /* Link layer / L2 overhead: Ethernet, 2 VLAN tags (C + S), FCS */ #define LIBETH_RX_LL_LEN (ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN) /* Maximum supported L2-L4 header length */ @@ -66,6 +68,7 @@ enum libeth_fqe_type { * @count: number of descriptors/buffers the queue has * @type: type of the buffers this queue has * @hsplit: flag whether header split is enabled + * @xdp: flag indicating whether XDP is enabled * @buf_len: HW-writeable length per each buffer * @nid: ID of the closest NUMA node with memory */ @@ -81,6 +84,7 @@ struct libeth_fq { /* Cold fields */ enum libeth_fqe_type type:2; bool hsplit:1; + bool xdp:1; u32 buf_len; int nid; -- 2.47.1