[PATCH net-next v3 0/4] Add the capability to consume SRAM for hwfd descriptor queue in airoha_eth driver

[PATCH net-next v3 0/4] Add the capability to consume SRAM for hwfd descriptor queue in airoha_eth driver

[Lorenzo Bianconi]

In order to improve packet processing and packet forwarding
performances, EN7581 SoC supports consuming SRAM instead of DRAM for hw
forwarding descriptors queue. For downlink hw accelerated traffic
request to consume SRAM memory for hw forwarding descriptors queue.
Moreover, in some configurations QDMA blocks require a contiguous block
of system memory for hwfd buffers queue. Introduce the capability to
allocate hw buffers forwarding queue via the reserved-memory DTS
property instead of running dmam_alloc_coherent().

---
Changes in v3:
- Remove hwfd references in airoha_qdma_struct in patch 2/4
- Split patch 2/2 in 3/4 and 4/4
- For downlink hw accelerated traffic request to consume SRAM memory for
  hw forwarding descriptors queue
- Fix comments
- Link to v2: https://lore.kernel.org/r/20250509-airopha-desc-sram-v2-0-9dc3d8076dfb@kernel.org

Changes in v2:
- fix sparse warnings
- Link to v1: https://lore.kernel.org/r/20250507-airopha-desc-sram-v1-0-d42037431bfa@kernel.org

---
Lorenzo Bianconi (4):
      dt-bindings: net: airoha: Add EN7581 memory-region property
      net: airoha: Do not store hfwd references in airoha_qdma struct
      net: airoha: Add the capability to allocate hwfd buffers via reserved-memory
      net: airoha: Add the capability to allocate hfwd descriptors in SRAM

 .../devicetree/bindings/net/airoha,en7581-eth.yaml | 13 ++++++
 drivers/net/ethernet/airoha/airoha_eth.c           | 50 ++++++++++++++--------
 drivers/net/ethernet/airoha/airoha_eth.h           | 15 ++++---
 drivers/net/ethernet/airoha/airoha_ppe.c           |  6 +++
 4 files changed, 60 insertions(+), 24 deletions(-)
---
base-commit: e6b3527c3b0a676c710e91798c2709cc0538d312
change-id: 20250507-airopha-desc-sram-faeb3ea6cbc5

Best regards,
-- 
Lorenzo Bianconi <lorenzo@kernel.org>

[PATCH net-next v3 1/4] dt-bindings: net: airoha: Add EN7581 memory-region property

[Lorenzo Bianconi]

Introduce memory-region and memory-region-names properties for the
ethernet node available on EN7581 SoC in order to reserve system memory
for hw forwarding buffers queue used by the QDMA modules.

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 .../devicetree/bindings/net/airoha,en7581-eth.yaml          | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
index 0fdd1126541774acacc783d98e4c089b2d2b85e2..6d22131ac2f9e28390b9e785ce33e8d983eafd0f 100644
--- a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
+++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
@@ -57,6 +57,16 @@ properties:
       - const: hsi-mac
       - const: xfp-mac
 
+  memory-region:
+    items:
+      - description: QDMA0 buffer memory
+      - description: QDMA1 buffer memory
+
+  memory-region-names:
+    items:
+      - const: qdma0-buf
+      - const: qdma1-buf
+
   "#address-cells":
     const: 1
 
@@ -140,6 +150,9 @@ examples:
                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
                      <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 
+        memory-region = <&qdma0_buf>, <&qdma1_buf>;
+        memory-region-names = "qdma0-buf", "qdma1-buf";
+
         airoha,npu = <&npu>;
 
         #address-cells = <1>;

-- 
2.49.0

Re: [PATCH net-next v3 1/4] dt-bindings: net: airoha: Add EN7581 memory-region property

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 388 bytes --]

On Wed, May 21, 2025 at 09:16:36AM +0200, Lorenzo Bianconi wrote:
> Introduce memory-region and memory-region-names properties for the
> ethernet node available on EN7581 SoC in order to reserve system memory
> for hw forwarding buffers queue used by the QDMA modules.
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH net-next v3 2/4] net: airoha: Do not store hfwd references in airoha_qdma struct

[Lorenzo Bianconi]

Since hfwd descriptor and buffer queues are allocated via
dmam_alloc_coherent() we do not need to store their references
in airoha_qdma struct. This patch does not introduce any logical changes,
just code clean-up.

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/net/ethernet/airoha/airoha_eth.c | 8 ++------
 drivers/net/ethernet/airoha/airoha_eth.h | 6 ------
 2 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 16c7896f931fd9532aa3b8cc78f41afc676aa117..5f7cbbcbb1d469836dfcea95137c960bfd076744 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -1081,17 +1081,13 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 	int size;
 
 	size = HW_DSCP_NUM * sizeof(struct airoha_qdma_fwd_desc);
-	qdma->hfwd.desc = dmam_alloc_coherent(eth->dev, size, &dma_addr,
-					      GFP_KERNEL);
-	if (!qdma->hfwd.desc)
+	if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))
 		return -ENOMEM;
 
 	airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
 
 	size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
-	qdma->hfwd.q = dmam_alloc_coherent(eth->dev, size, &dma_addr,
-					   GFP_KERNEL);
-	if (!qdma->hfwd.q)
+	if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))
 		return -ENOMEM;
 
 	airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr);
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 531a3c49c1562a986111a1ce1c215c8751c16e09..3e03ae9a5d0d21c0d8d717f2a282ff06ef3b9fbf 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -513,12 +513,6 @@ struct airoha_qdma {
 
 	struct airoha_queue q_tx[AIROHA_NUM_TX_RING];
 	struct airoha_queue q_rx[AIROHA_NUM_RX_RING];
-
-	/* descriptor and packet buffers for qdma hw forward */
-	struct {
-		void *desc;
-		void *q;
-	} hfwd;
 };
 
 struct airoha_gdm_port {

-- 
2.49.0

Re: [PATCH net-next v3 2/4] net: airoha: Do not store hfwd references in airoha_qdma struct

[Simon Horman]

On Wed, May 21, 2025 at 09:16:37AM +0200, Lorenzo Bianconi wrote:
> Since hfwd descriptor and buffer queues are allocated via
> dmam_alloc_coherent() we do not need to store their references
> in airoha_qdma struct. This patch does not introduce any logical changes,
> just code clean-up.
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>

Reviewed-by: Simon Horman <horms@kernel.org>

[PATCH net-next v3 3/4] net: airoha: Add the capability to allocate hwfd buffers via reserved-memory

[Lorenzo Bianconi]

In some configurations QDMA blocks require a contiguous block of
system memory for hwfd buffers queue. Introduce the capability to allocate
hw buffers forwarding queue via the reserved-memory DTS property instead of
running dmam_alloc_coherent().

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/net/ethernet/airoha/airoha_eth.c | 33 +++++++++++++++++++++++++++++---
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 5f7cbbcbb1d469836dfcea95137c960bfd076744..20e590d76735e72a1a538a42d2a1f49b882deccc 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -5,6 +5,7 @@
  */
 #include <linux/of.h>
 #include <linux/of_net.h>
+#include <linux/of_reserved_mem.h>
 #include <linux/platform_device.h>
 #include <linux/tcp.h>
 #include <linux/u64_stats_sync.h>
@@ -1076,9 +1077,11 @@ static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 {
 	struct airoha_eth *eth = qdma->eth;
+	int id = qdma - &eth->qdma[0];
 	dma_addr_t dma_addr;
+	const char *name;
+	int size, index;
 	u32 status;
-	int size;
 
 	size = HW_DSCP_NUM * sizeof(struct airoha_qdma_fwd_desc);
 	if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))
@@ -1086,10 +1089,34 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 
 	airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
 
-	size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
-	if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))
+	name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id);
+	if (!name)
 		return -ENOMEM;
 
+	index = of_property_match_string(eth->dev->of_node,
+					 "memory-region-names", name);
+	if (index >= 0) {
+		struct reserved_mem *rmem;
+		struct device_node *np;
+
+		/* Consume reserved memory for hw forwarding buffers queue if
+		 * available in the DTS
+		 */
+		np = of_parse_phandle(eth->dev->of_node, "memory-region",
+				      index);
+		if (!np)
+			return -ENODEV;
+
+		rmem = of_reserved_mem_lookup(np);
+		of_node_put(np);
+		dma_addr = rmem->base;
+	} else {
+		size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
+		if (!dmam_alloc_coherent(eth->dev, size, &dma_addr,
+					 GFP_KERNEL))
+			return -ENOMEM;
+	}
+
 	airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr);
 
 	airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG,

-- 
2.49.0

Re: [PATCH net-next v3 3/4] net: airoha: Add the capability to allocate hwfd buffers via reserved-memory

[Simon Horman]

On Wed, May 21, 2025 at 09:16:38AM +0200, Lorenzo Bianconi wrote:
> In some configurations QDMA blocks require a contiguous block of
> system memory for hwfd buffers queue. Introduce the capability to allocate
> hw buffers forwarding queue via the reserved-memory DTS property instead of
> running dmam_alloc_coherent().
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>

Reviewed-by: Simon Horman <horms@kernel.org>

[PATCH net-next v3 4/4] net: airoha: Add the capability to allocate hfwd descriptors in SRAM

[Lorenzo Bianconi]

In order to improve packet processing and packet forwarding
performances, EN7581 SoC supports consuming SRAM instead of DRAM for
hw forwarding descriptors queue.
For downlink hw accelerated traffic request to consume SRAM memory
for hw forwarding descriptors queue.

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/net/ethernet/airoha/airoha_eth.c | 11 +----------
 drivers/net/ethernet/airoha/airoha_eth.h |  9 +++++++++
 drivers/net/ethernet/airoha/airoha_ppe.c |  6 ++++++
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 20e590d76735e72a1a538a42d2a1f49b882deccc..3cd56de716a5269b1530cff6d0ca3414d92ecb69 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -71,15 +71,6 @@ static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,
 	airoha_qdma_set_irqmask(irq_bank, index, mask, 0);
 }
 
-static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
-{
-	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
-	 * GDM{2,3,4} can be used as wan port connected to an external
-	 * phy module.
-	 */
-	return port->id == 1;
-}
-
 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
 {
 	struct airoha_eth *eth = port->qdma->eth;
@@ -1128,7 +1119,7 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
 			LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
 			HW_FWD_DESC_NUM_MASK,
 			FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
-			LMGR_INIT_START);
+			LMGR_INIT_START | LMGR_SRAM_MODE_MASK);
 
 	return read_poll_timeout(airoha_qdma_rr, status,
 				 !(status & LMGR_INIT_START), USEC_PER_MSEC,
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 3e03ae9a5d0d21c0d8d717f2a282ff06ef3b9fbf..b815697302bfdf2a6d115a9bbbbadc05462dbadb 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -597,6 +597,15 @@ u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
 #define airoha_qdma_clear(qdma, offset, val)			\
 	airoha_rmw((qdma)->regs, (offset), (val), 0)
 
+static inline bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
+{
+	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
+	 * GDM{2,3,4} can be used as wan port connected to an external
+	 * phy module.
+	 */
+	return port->id == 1;
+}
+
 bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
 			      struct airoha_gdm_port *port);
 
diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index 2d273937f19cf304ab4b821241fdc3ea93604f0e..12d32c92717a6b4ba74728ec02bb2e166d4d9407 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -251,6 +251,12 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
 		else
 			pse_port = 2; /* uplink relies on GDM2 loopback */
 		val |= FIELD_PREP(AIROHA_FOE_IB2_PSE_PORT, pse_port);
+
+		/* For downlink traffic consume SRAM memory for hw forwarding
+		 * descriptors queue.
+		 */
+		if (airhoa_is_lan_gdm_port(port))
+			val |= AIROHA_FOE_IB2_FAST_PATH;
 	}
 
 	if (is_multicast_ether_addr(data->eth.h_dest))

-- 
2.49.0

Re: [PATCH net-next v3 4/4] net: airoha: Add the capability to allocate hfwd descriptors in SRAM

[Simon Horman]

On Wed, May 21, 2025 at 09:16:39AM +0200, Lorenzo Bianconi wrote:
> In order to improve packet processing and packet forwarding
> performances, EN7581 SoC supports consuming SRAM instead of DRAM for
> hw forwarding descriptors queue.
> For downlink hw accelerated traffic request to consume SRAM memory
> for hw forwarding descriptors queue.
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>  drivers/net/ethernet/airoha/airoha_eth.c | 11 +----------
>  drivers/net/ethernet/airoha/airoha_eth.h |  9 +++++++++
>  drivers/net/ethernet/airoha/airoha_ppe.c |  6 ++++++
>  3 files changed, 16 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index 20e590d76735e72a1a538a42d2a1f49b882deccc..3cd56de716a5269b1530cff6d0ca3414d92ecb69 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -71,15 +71,6 @@ static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,
>  	airoha_qdma_set_irqmask(irq_bank, index, mask, 0);
>  }
>  
> -static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
> -{
> -	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
> -	 * GDM{2,3,4} can be used as wan port connected to an external
> -	 * phy module.
> -	 */
> -	return port->id == 1;
> -}
> -
>  static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
>  {
>  	struct airoha_eth *eth = port->qdma->eth;
> @@ -1128,7 +1119,7 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
>  			LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
>  			HW_FWD_DESC_NUM_MASK,
>  			FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
> -			LMGR_INIT_START);
> +			LMGR_INIT_START | LMGR_SRAM_MODE_MASK);

Hi Lorenzo,

I'm wondering if setting the LMGR_SRAM_MODE_MASK bit (maybe a different
name for the #define would be nice) is dependent on the SRAM region
being described in DT, as per code added above this line to this
function by the previous patch in this series.

>  
>  	return read_poll_timeout(airoha_qdma_rr, status,
>  				 !(status & LMGR_INIT_START), USEC_PER_MSEC,
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> index 3e03ae9a5d0d21c0d8d717f2a282ff06ef3b9fbf..b815697302bfdf2a6d115a9bbbbadc05462dbadb 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.h
> +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> @@ -597,6 +597,15 @@ u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
>  #define airoha_qdma_clear(qdma, offset, val)			\
>  	airoha_rmw((qdma)->regs, (offset), (val), 0)
>  
> +static inline bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
> +{
> +	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
> +	 * GDM{2,3,4} can be used as wan port connected to an external
> +	 * phy module.
> +	 */
> +	return port->id == 1;
> +}
> +
>  bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
>  			      struct airoha_gdm_port *port);
>  
> diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
> index 2d273937f19cf304ab4b821241fdc3ea93604f0e..12d32c92717a6b4ba74728ec02bb2e166d4d9407 100644
> --- a/drivers/net/ethernet/airoha/airoha_ppe.c
> +++ b/drivers/net/ethernet/airoha/airoha_ppe.c
> @@ -251,6 +251,12 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
>  		else
>  			pse_port = 2; /* uplink relies on GDM2 loopback */
>  		val |= FIELD_PREP(AIROHA_FOE_IB2_PSE_PORT, pse_port);
> +
> +		/* For downlink traffic consume SRAM memory for hw forwarding
> +		 * descriptors queue.
> +		 */
> +		if (airhoa_is_lan_gdm_port(port))
> +			val |= AIROHA_FOE_IB2_FAST_PATH;
>  	}
>  
>  	if (is_multicast_ether_addr(data->eth.h_dest))
> 
> -- 
> 2.49.0
> 
> 

Re: [PATCH net-next v3 4/4] net: airoha: Add the capability to allocate hfwd descriptors in SRAM

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 4583 bytes --]

> On Wed, May 21, 2025 at 09:16:39AM +0200, Lorenzo Bianconi wrote:
> > In order to improve packet processing and packet forwarding
> > performances, EN7581 SoC supports consuming SRAM instead of DRAM for
> > hw forwarding descriptors queue.
> > For downlink hw accelerated traffic request to consume SRAM memory
> > for hw forwarding descriptors queue.
> > 
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >  drivers/net/ethernet/airoha/airoha_eth.c | 11 +----------
> >  drivers/net/ethernet/airoha/airoha_eth.h |  9 +++++++++
> >  drivers/net/ethernet/airoha/airoha_ppe.c |  6 ++++++
> >  3 files changed, 16 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> > index 20e590d76735e72a1a538a42d2a1f49b882deccc..3cd56de716a5269b1530cff6d0ca3414d92ecb69 100644
> > --- a/drivers/net/ethernet/airoha/airoha_eth.c
> > +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> > @@ -71,15 +71,6 @@ static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,
> >  	airoha_qdma_set_irqmask(irq_bank, index, mask, 0);
> >  }
> >  
> > -static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
> > -{
> > -	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
> > -	 * GDM{2,3,4} can be used as wan port connected to an external
> > -	 * phy module.
> > -	 */
> > -	return port->id == 1;
> > -}
> > -
> >  static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
> >  {
> >  	struct airoha_eth *eth = port->qdma->eth;
> > @@ -1128,7 +1119,7 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
> >  			LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
> >  			HW_FWD_DESC_NUM_MASK,
> >  			FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
> > -			LMGR_INIT_START);
> > +			LMGR_INIT_START | LMGR_SRAM_MODE_MASK);
> 
> Hi Lorenzo,

Hi Simon,

> 
> I'm wondering if setting the LMGR_SRAM_MODE_MASK bit (maybe a different
> name for the #define would be nice) is dependent on the SRAM region

I did this way because LMGR_SRAM_MODE_MASK is just a bit. Do you prefer
to do something like:

FIELD_PREP(LMGR_SRAM_MODE_MASK, 1)?

> being described in DT, as per code added above this line to this
> function by the previous patch in this series.

Are you referring to qdma0_buf/qdma1_buf memory regions?
https://patchwork.kernel.org/project/netdevbpf/patch/20250521-airopha-desc-sram-v3-1-a6e9b085b4f0@kernel.org/

If so, they are DRAM memory-regions and not SRAM ones. They are used for
hw forwarding buffers queue. SRAM is used for hw forwarding descriptor queue.

Regards,
Lorenzo

> 
> >  
> >  	return read_poll_timeout(airoha_qdma_rr, status,
> >  				 !(status & LMGR_INIT_START), USEC_PER_MSEC,
> > diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> > index 3e03ae9a5d0d21c0d8d717f2a282ff06ef3b9fbf..b815697302bfdf2a6d115a9bbbbadc05462dbadb 100644
> > --- a/drivers/net/ethernet/airoha/airoha_eth.h
> > +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> > @@ -597,6 +597,15 @@ u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
> >  #define airoha_qdma_clear(qdma, offset, val)			\
> >  	airoha_rmw((qdma)->regs, (offset), (val), 0)
> >  
> > +static inline bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
> > +{
> > +	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
> > +	 * GDM{2,3,4} can be used as wan port connected to an external
> > +	 * phy module.
> > +	 */
> > +	return port->id == 1;
> > +}
> > +
> >  bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
> >  			      struct airoha_gdm_port *port);
> >  
> > diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
> > index 2d273937f19cf304ab4b821241fdc3ea93604f0e..12d32c92717a6b4ba74728ec02bb2e166d4d9407 100644
> > --- a/drivers/net/ethernet/airoha/airoha_ppe.c
> > +++ b/drivers/net/ethernet/airoha/airoha_ppe.c
> > @@ -251,6 +251,12 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
> >  		else
> >  			pse_port = 2; /* uplink relies on GDM2 loopback */
> >  		val |= FIELD_PREP(AIROHA_FOE_IB2_PSE_PORT, pse_port);
> > +
> > +		/* For downlink traffic consume SRAM memory for hw forwarding
> > +		 * descriptors queue.
> > +		 */
> > +		if (airhoa_is_lan_gdm_port(port))
> > +			val |= AIROHA_FOE_IB2_FAST_PATH;
> >  	}
> >  
> >  	if (is_multicast_ether_addr(data->eth.h_dest))
> > 
> > -- 
> > 2.49.0
> > 
> > 

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Re: [PATCH net-next v3 4/4] net: airoha: Add the capability to allocate hfwd descriptors in SRAM

[Simon Horman]

On Thu, May 22, 2025 at 02:58:56PM +0200, Lorenzo Bianconi wrote:
> > On Wed, May 21, 2025 at 09:16:39AM +0200, Lorenzo Bianconi wrote:
> > > In order to improve packet processing and packet forwarding
> > > performances, EN7581 SoC supports consuming SRAM instead of DRAM for
> > > hw forwarding descriptors queue.
> > > For downlink hw accelerated traffic request to consume SRAM memory
> > > for hw forwarding descriptors queue.
> > > 
> > > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > > ---
> > >  drivers/net/ethernet/airoha/airoha_eth.c | 11 +----------
> > >  drivers/net/ethernet/airoha/airoha_eth.h |  9 +++++++++
> > >  drivers/net/ethernet/airoha/airoha_ppe.c |  6 ++++++
> > >  3 files changed, 16 insertions(+), 10 deletions(-)
> > > 
> > > diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> > > index 20e590d76735e72a1a538a42d2a1f49b882deccc..3cd56de716a5269b1530cff6d0ca3414d92ecb69 100644
> > > --- a/drivers/net/ethernet/airoha/airoha_eth.c
> > > +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> > > @@ -71,15 +71,6 @@ static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,
> > >  	airoha_qdma_set_irqmask(irq_bank, index, mask, 0);
> > >  }
> > >  
> > > -static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port)
> > > -{
> > > -	/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
> > > -	 * GDM{2,3,4} can be used as wan port connected to an external
> > > -	 * phy module.
> > > -	 */
> > > -	return port->id == 1;
> > > -}
> > > -
> > >  static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
> > >  {
> > >  	struct airoha_eth *eth = port->qdma->eth;
> > > @@ -1128,7 +1119,7 @@ static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
> > >  			LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
> > >  			HW_FWD_DESC_NUM_MASK,
> > >  			FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
> > > -			LMGR_INIT_START);
> > > +			LMGR_INIT_START | LMGR_SRAM_MODE_MASK);
> > 
> > Hi Lorenzo,
> 
> Hi Simon,
> 
> > 
> > I'm wondering if setting the LMGR_SRAM_MODE_MASK bit (maybe a different
> > name for the #define would be nice) is dependent on the SRAM region
> 
> I did this way because LMGR_SRAM_MODE_MASK is just a bit. Do you prefer
> to do something like:
> 
> FIELD_PREP(LMGR_SRAM_MODE_MASK, 1)?

Let's leave it as you have it in this patch :)

> 
> > being described in DT, as per code added above this line to this
> > function by the previous patch in this series.
> 
> Are you referring to qdma0_buf/qdma1_buf memory regions?
> https://patchwork.kernel.org/project/netdevbpf/patch/20250521-airopha-desc-sram-v3-1-a6e9b085b4f0@kernel.org/
> 
> If so, they are DRAM memory-regions and not SRAM ones. They are used for
> hw forwarding buffers queue. SRAM is used for hw forwarding descriptor queue.

Yes, my mistake.

With that cleared up I think this patch looks good.

Reviewed-by: Simon Horman <horms@kernel.org>

Re: [PATCH net-next v3 0/4] Add the capability to consume SRAM for hwfd descriptor queue in airoha_eth driver

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net-next.git (main)
by Paolo Abeni <pabeni@redhat.com>:

On Wed, 21 May 2025 09:16:35 +0200 you wrote:
> In order to improve packet processing and packet forwarding
> performances, EN7581 SoC supports consuming SRAM instead of DRAM for hw
> forwarding descriptors queue. For downlink hw accelerated traffic
> request to consume SRAM memory for hw forwarding descriptors queue.
> Moreover, in some configurations QDMA blocks require a contiguous block
> of system memory for hwfd buffers queue. Introduce the capability to
> allocate hw buffers forwarding queue via the reserved-memory DTS
> property instead of running dmam_alloc_coherent().
> 
> [...]

Here is the summary with links:
  - [net-next,v3,1/4] dt-bindings: net: airoha: Add EN7581 memory-region property
    https://git.kernel.org/netdev/net-next/c/2d13b45f8086
  - [net-next,v3,2/4] net: airoha: Do not store hfwd references in airoha_qdma struct
    https://git.kernel.org/netdev/net-next/c/09aa788f98da
  - [net-next,v3,3/4] net: airoha: Add the capability to allocate hwfd buffers via reserved-memory
    https://git.kernel.org/netdev/net-next/c/3a1ce9e3d01b
  - [net-next,v3,4/4] net: airoha: Add the capability to allocate hfwd descriptors in SRAM
    https://git.kernel.org/netdev/net-next/c/c683e378c090

You are awesome, thank you!
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