Re: [PATCH v2] dt-bindings: net: Convert socfpga-dwmac bindings to yaml

[Maxime Chevallier <maxime.chevallier@bootlin.com>]

Hello Matthew,

On Wed, 28 May 2025 07:46:50 -0700
Matthew Gerlach <matthew.gerlach@altera.com> wrote:

> From: Mun Yew Tham <mun.yew.tham@altera.com>
> 
> Convert the bindings for socfpga-dwmac to yaml.

Oh nice ! Thanks for doing that ! I had some very distant plans to do
that at some point, but it was way down my priority list :( I'll try to
help the best I can !

> Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> ---
> v2:
>  - Add compatible to required.
>  - Add descriptions for clocks.
>  - Add clock-names.
>  - Clean up items: in altr,sysmgr-syscon.
>  - Change "additionalProperties: true" to "unevaluatedProperties: false".
>  - Add properties needed for "unevaluatedProperties: false".
>  - Fix indentation in examples.
>  - Drop gmac0: label in examples.
>  - Exclude support for Arria10 that is not validating.
> ---
>  .../bindings/net/socfpga,dwmac.yaml           | 148 ++++++++++++++++++
>  .../devicetree/bindings/net/socfpga-dwmac.txt |  57 -------
>  2 files changed, 148 insertions(+), 57 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/net/socfpga,dwmac.yaml
>  delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt
> 
> diff --git a/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml b/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml
> new file mode 100644
> index 000000000000..a02175838fba
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml
> @@ -0,0 +1,148 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/socfpga,dwmac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera SOCFPGA SoC DWMAC controller
> +
> +maintainers:
> +  - Matthew Gerlach <matthew.gerlach@altera.com>
> +
> +description:
> +  This binding describes the Altera SOCFPGA SoC implementation of the
> +  Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, and Agilex7 families
> +  of chips.
> +  # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
> +  # does not validate against net/snps,dwmac.yaml.
> +
> +select:
> +  properties:
> +    compatible:
> +      oneOf:
> +        - items:
> +            - const: altr,socfpga-stmmac
> +            - const: snps,dwmac-3.70a
> +            - const: snps,dwmac
> +        - items:
> +            - const: altr,socfpga-stmmac-a10-s10
> +            - const: snps,dwmac-3.74a
> +            - const: snps,dwmac
> +
> +  required:
> +    - compatible
> +    - altr,sysmgr-syscon
> +
> +properties:
> +  clocks:
> +    minItems: 1
> +    items:
> +      - description: GMAC main clock
> +      - description:
> +          PTP reference clock. This clock is used for programming the
> +          Timestamp Addend Register. If not passed then the system
> +          clock will be used and this is fine on some platforms.
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 2
> +    contains:
> +      enum:
> +        - stmmaceth
> +        - ptp_ref
> +
> +  iommus:
> +    maxItems: 1
> +
> +  phy-mode:
> +    enum:
> +      - rgmii

You're missing rgmii-id, rgmii-rxid and rgmii-txid

> +      - sgmii

SGMII is only supported when we have the optional
altr,gmii-to-sgmii-converter phandle, but I am pretty bad at writing
binding, I don't really know how to express this kind of constraint :/

1000base-x is also supported if the gmii-to-sgmii adapter supports it
as well, by having a TSE PCS (Lynx) included.

> +      - gmii

rmii and mii are also supported, it would make sense to add it
here.

Maxime