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[2a02:9142:4580:1200::8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450d8000d5dsm44500205e9.26.2025.05.31.03.13.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 May 2025 03:13:24 -0700 (PDT) From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= To: jonas.gorski@gmail.com, florian.fainelli@broadcom.com, andrew@lunn.ch, olteanv@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, vivien.didelot@gmail.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, dgcbueu@gmail.com Cc: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Subject: [RFC PATCH 08/10] net: dsa: b53: fix unicast/multicast flooding on BCM5325 Date: Sat, 31 May 2025 12:13:06 +0200 Message-Id: <20250531101308.155757-9-noltari@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250531101308.155757-1-noltari@gmail.com> References: <20250531101308.155757-1-noltari@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM5325 doesn't implement UC_FLOOD_MASK, MC_FLOOD_MASK and IPMC_FLOOD_MASK registers. This has to be handled differently with other pages and registers. Fixes: a8b659e7ff75 ("net: dsa: act as passthrough for bridge port flags") Signed-off-by: Álvaro Fernández Rojas --- drivers/net/dsa/b53/b53_common.c | 85 +++++++++++++++++++++++++------- drivers/net/dsa/b53/b53_regs.h | 38 ++++++++++++++ 2 files changed, 105 insertions(+), 18 deletions(-) diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_common.c index 387e1e7ec749..d5216ea2c984 100644 --- a/drivers/net/dsa/b53/b53_common.c +++ b/drivers/net/dsa/b53/b53_common.c @@ -560,12 +560,36 @@ static void b53_port_set_ucast_flood(struct b53_device *dev, int port, { u16 uc; - b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); - if (unicast) - uc |= BIT(port); - else - uc &= ~BIT(port); - b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); + if (is5325(dev)) { + u8 rc; + + if (port == B53_CPU_PORT_25) + port = B53_CPU_PORT; + + b53_read16(dev, B53_IEEE_PAGE, B53_IEEE_UCAST_DLF, &uc); + if (unicast) + uc |= BIT(port) | B53_IEEE_UCAST_DROP_EN; + else + uc &= ~BIT(port); + b53_write16(dev, B53_IEEE_PAGE, B53_IEEE_UCAST_DLF, uc); + + if (port >= B53_CPU_PORT_25) + return; + + b53_read8(dev, B53_RATE_CTL_PAGE, B53_RATE_CONTROL(port), &rc); + if (unicast) + rc |= (RC_DLF_EN | RC_BKT_SIZE_8K | RC_PERCENT_40); + else + rc &= ~(RC_DLF_EN); + b53_write8(dev, B53_RATE_CTL_PAGE, B53_RATE_CONTROL(port), rc); + } else { + b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); + if (unicast) + uc |= BIT(port); + else + uc &= ~BIT(port); + b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); + } } static void b53_port_set_mcast_flood(struct b53_device *dev, int port, @@ -573,19 +597,44 @@ static void b53_port_set_mcast_flood(struct b53_device *dev, int port, { u16 mc; - b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); - if (multicast) - mc |= BIT(port); - else - mc &= ~BIT(port); - b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); + if (is5325(dev)) { + u8 rc; - b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); - if (multicast) - mc |= BIT(port); - else - mc &= ~BIT(port); - b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); + if (port == B53_CPU_PORT_25) + port = B53_CPU_PORT; + + b53_read16(dev, B53_IEEE_PAGE, B53_IEEE_MCAST_DLF, &mc); + if (multicast) + mc |= BIT(port) | B53_IEEE_MCAST_DROP_EN; + else + mc &= ~BIT(port); + b53_write16(dev, B53_IEEE_PAGE, B53_IEEE_MCAST_DLF, mc); + + if (port >= B53_CPU_PORT_25) + return; + + b53_read8(dev, B53_RATE_CTL_PAGE, B53_RATE_CONTROL(port), &rc); + if (multicast) + rc |= (RC_BCAST_EN | RC_MCAST_EN | RC_BKT_SIZE_8K | + RC_PERCENT_40); + else + rc &= ~(RC_BCAST_EN | RC_MCAST_EN); + b53_write8(dev, B53_RATE_CTL_PAGE, B53_RATE_CONTROL(port), rc); + } else { + b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); + if (multicast) + mc |= BIT(port); + else + mc &= ~BIT(port); + b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); + + b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); + if (multicast) + mc |= BIT(port); + else + mc &= ~BIT(port); + b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); + } } static void b53_port_set_learning(struct b53_device *dev, int port, diff --git a/drivers/net/dsa/b53/b53_regs.h b/drivers/net/dsa/b53/b53_regs.h index ab15f36a135a..b0a7ba3d9b65 100644 --- a/drivers/net/dsa/b53/b53_regs.h +++ b/drivers/net/dsa/b53/b53_regs.h @@ -29,6 +29,7 @@ #define B53_ARLIO_PAGE 0x05 /* ARL Access */ #define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */ #define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */ +#define B53_IEEE_PAGE 0x0a /* IEEE 802.1X */ /* PHY Registers */ #define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */ @@ -47,6 +48,9 @@ /* VLAN Registers */ #define B53_VLAN_PAGE 0x34 +/* Rate Control Registers */ +#define B53_RATE_CTL_PAGE 0x35 + /* Jumbo Frame Registers */ #define B53_JUMBO_PAGE 0x40 @@ -368,6 +372,18 @@ #define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10)) #define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10)) +/************************************************************************* + * IEEE 802.1X Registers + *************************************************************************/ + +/* Multicast DLF Drop Control register (16 bit) */ +#define B53_IEEE_MCAST_DLF 0x94 +#define B53_IEEE_MCAST_DROP_EN BIT(11) + +/* Unicast DLF Drop Control register (16 bit) */ +#define B53_IEEE_UCAST_DLF 0x96 +#define B53_IEEE_UCAST_DROP_EN BIT(11) + /************************************************************************* * Port VLAN Registers *************************************************************************/ @@ -478,6 +494,28 @@ /* VLAN Port Default Tag (16 bit) */ #define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i)) +/************************************************************************* + * Rate Control Page Registers + *************************************************************************/ + +#define B53_RATE_CONTROL(i) (0x00 + (i)) +#define RC_PERCENT_S 0 +#define RC_PERCENT_10 (0 << RC_PERCENT_S) +#define RC_PERCENT_20 (1 << RC_PERCENT_S) +#define RC_PERCENT_30 (2 << RC_PERCENT_S) +#define RC_PERCENT_40 (3 << RC_PERCENT_S) +#define RC_PERCENT_MASK (3 << RC_PERCENT_S) +#define RC_BKT_SIZE_S 2 +#define RC_BKT_SIZE_2K (0 << RC_BKT_SIZE_S) +#define RC_BKT_SIZE_4K (1 << RC_BKT_SIZE_S) +#define RC_BKT_SIZE_6K (2 << RC_BKT_SIZE_S) +#define RC_BKT_SIZE_8K (3 << RC_BKT_SIZE_S) +#define RC_BKT_SIZE_MASK (3 << RC_BKT_SIZE_S) +#define RC_DLF_EN BIT(4) +#define RC_BCAST_EN BIT(5) +#define RC_MCAST_EN BIT(6) +#define RC_DROP_FRAME BIT(7) + /************************************************************************* * Jumbo Frame Page Registers *************************************************************************/ -- 2.39.5