[PATCH 3/3] cxgb3: Split complex PCI write statement into logic + write

["Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>]

Instead of trying to complex logic within the PCI capability write
statement, split the logic onto separate lines for better readability.
Also, don't pretend just clearing the fields, but set the fields to
what 0 means (128 bytes).

Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
index 171bf6cf1abf..b9327d8c6893 100644
--- a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
@@ -3267,9 +3267,9 @@ static void config_pcie(struct adapter *adap)
 
 	pci_read_config_word(adap->pdev, PCI_DEVICE_ID, &devid);
 	if (devid == 0x37) {
-		pcie_capability_write_word(adap->pdev, PCI_EXP_DEVCTL,
-					   val & ~PCI_EXP_DEVCTL_READRQ &
-					   ~PCI_EXP_DEVCTL_PAYLOAD);
+		val &= ~(PCI_EXP_DEVCTL_PAYLOAD|PCI_EXP_DEVCTL_READRQ);
+		val |= PCI_EXP_DEVCTL_PAYLOAD_128B|PCI_EXP_DEVCTL_READRQ_128B;
+		pcie_capability_write_word(adap->pdev, PCI_EXP_DEVCTL, val);
 		pldsize = 0;
 	}
 
-- 
2.39.5