From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0F3D244678 for ; Wed, 11 Jun 2025 18:03:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749665009; cv=none; b=OvBIcSH+OYbNU8IKiRZhSs/4NEo//9f1mYdReBkhOYvDI/iF2HtA09oV+/mThOJNGIAUPPuk87HpD9GUWwYOQbCEoAwSjff19Q8eWLo9d8yhILabV532Cg52WCQ2jcLqwflJj9jgb56ki/GaDzoM7Jbv4lgZ0ZDkNKYVmDiyY1A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749665009; c=relaxed/simple; bh=wZYTxGUZv78C82SY1xo7rOP+ANGK3VjcM19OXzFQygo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qf8gn+Q8lCuX+gjj/CyglMT+zUftbRCnSZXwzf29N+a9nYK7XMUZaIpUmmy5KXH2GDC9djRMLVdZ13ZgCJ3ikLz2aiflhp1CHbK0YFpinm3e0DKanF+2SrVCmEP4BqFduN40XMgrJB2g1IIwjQgfsWkrE7wMFP95A2n/Vi6WegY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=m1WbLLVO; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="m1WbLLVO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1749665008; x=1781201008; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wZYTxGUZv78C82SY1xo7rOP+ANGK3VjcM19OXzFQygo=; b=m1WbLLVOEA8hkweyIDsxU1ZKtl5twhQRQ4lqqD99zcSmxBSheb7PHsnn /tz4kzorAjQOxlwRZWaiSeqwbFazP7rgIEic+IH/dncjyPsszTuAeeZEl uuWmAA01K3PuhiaWF1vmZuQNeXwBbeyRTr/wtY1ai1lA2Oo4UgDZ9rT9S 10VXgtgFLxJFI7JpR/GvKkagGLKlyQII8tef/vEuCPsazR7TcrpTLA72Z jTcwGG3BMyV6DK+isvh9+I2/tYzJd1MNNTUitaYYYqmGYF9sRU16QqSg1 yle7FJ9sxmCL0Lne8Yb6fJOMMQotRtGOtzDM+J0GnqqGbya7Yg+trxxdf A==; X-CSE-ConnectionGUID: I1g5mDpzRnSUcXgh5PVb/g== X-CSE-MsgGUID: wimmRmxRSC21Lskuc40dyw== X-IronPort-AV: E=McAfee;i="6800,10657,11461"; a="51042553" X-IronPort-AV: E=Sophos;i="6.16,228,1744095600"; d="scan'208";a="51042553" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2025 11:03:27 -0700 X-CSE-ConnectionGUID: oferskOXRWWi0YBRmhWpxQ== X-CSE-MsgGUID: wAdy1GD+Tn6+9BzhobUWcA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,228,1744095600"; d="scan'208";a="152418273" Received: from anguy11-upstream.jf.intel.com ([10.166.9.133]) by fmviesa004.fm.intel.com with ESMTP; 11 Jun 2025 11:03:26 -0700 From: Tony Nguyen To: davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, edumazet@google.com, andrew+netdev@lunn.ch, netdev@vger.kernel.org Cc: Faizal Rahim , anthony.l.nguyen@intel.com, faizal.abdul.rahim@intel.com, chwee.lin.choong@intel.com, vladimir.oltean@nxp.com, horms@kernel.org, vitaly.lifshits@intel.com, dima.ruinskiy@intel.com, Mor Bar-Gabay Subject: [PATCH net-next 3/7] igc: refactor TXDCTL macros to use FIELD_PREP and GEN_MASK Date: Wed, 11 Jun 2025 11:03:05 -0700 Message-ID: <20250611180314.2059166-4-anthony.l.nguyen@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250611180314.2059166-1-anthony.l.nguyen@intel.com> References: <20250611180314.2059166-1-anthony.l.nguyen@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Faizal Rahim Refactor TXDCTL macro handling to use FIELD_PREP and GENMASK macros. This prepares the code for adding a new TXDCTL priority field in an upcoming patch. Verified that the macro values remain unchanged before and after refactoring. Reviewed-by: Simon Horman Signed-off-by: Faizal Rahim Tested-by: Mor Bar-Gabay Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/igc/igc.h | 15 ++++++++++----- drivers/net/ethernet/intel/igc/igc_main.c | 6 ++---- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h index db1e2db1619e..daab06fc3f80 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -493,13 +493,18 @@ static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc) /* Receive Software Flush */ #define IGC_RXDCTL_SWFLUSH 0x04000000 -#define IGC_TXDCTL_PTHRESH 8 -#define IGC_TXDCTL_HTHRESH 1 -#define IGC_TXDCTL_WTHRESH 16 +#define IGC_TXDCTL_PTHRESH_MASK GENMASK(4, 0) +#define IGC_TXDCTL_HTHRESH_MASK GENMASK(12, 8) +#define IGC_TXDCTL_WTHRESH_MASK GENMASK(20, 16) +#define IGC_TXDCTL_QUEUE_ENABLE_MASK GENMASK(25, 25) +#define IGC_TXDCTL_SWFLUSH_MASK GENMASK(26, 26) +#define IGC_TXDCTL_PTHRESH(x) FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x)) +#define IGC_TXDCTL_HTHRESH(x) FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x)) +#define IGC_TXDCTL_WTHRESH(x) FIELD_PREP(IGC_TXDCTL_WTHRESH_MASK, (x)) /* Ena specific Tx Queue */ -#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 +#define IGC_TXDCTL_QUEUE_ENABLE FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, 1) /* Transmit Software Flush */ -#define IGC_TXDCTL_SWFLUSH 0x04000000 +#define IGC_TXDCTL_SWFLUSH FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1) #define IGC_RX_DMA_ATTR \ (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c index 4f1a8bc006c6..f3a312c9413b 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -749,11 +749,9 @@ static void igc_configure_tx_ring(struct igc_adapter *adapter, wr32(IGC_TDH(reg_idx), 0); writel(0, ring->tail); - txdctl |= IGC_TXDCTL_PTHRESH; - txdctl |= IGC_TXDCTL_HTHRESH << 8; - txdctl |= IGC_TXDCTL_WTHRESH << 16; + txdctl |= IGC_TXDCTL_PTHRESH(8) | IGC_TXDCTL_HTHRESH(1) | + IGC_TXDCTL_WTHRESH(16) | IGC_TXDCTL_QUEUE_ENABLE; - txdctl |= IGC_TXDCTL_QUEUE_ENABLE; wr32(IGC_TXDCTL(reg_idx), txdctl); } -- 2.47.1