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From: Simon Horman <horms@kernel.org>
To: Ivan Vecera <ivecera@redhat.com>
Cc: netdev@vger.kernel.org,
	Prathosh Satish <Prathosh.Satish@microchip.com>,
	Vadim Fedorenko <vadim.fedorenko@linux.dev>,
	Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
	Jiri Pirko <jiri@resnulli.us>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Jonathan Corbet <corbet@lwn.net>, Jason Gunthorpe <jgg@ziepe.ca>,
	Shannon Nelson <shannon.nelson@amd.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-doc@vger.kernel.org, Michal Schmidt <mschmidt@redhat.com>,
	Petr Oros <poros@redhat.com>
Subject: Re: [PATCH net-next v10 09/14] dpll: zl3073x: Register DPLL devices and pins
Date: Mon, 16 Jun 2025 17:00:47 +0100	[thread overview]
Message-ID: <20250616160047.GG6918@horms.kernel.org> (raw)
In-Reply-To: <20250615201223.1209235-10-ivecera@redhat.com>

On Sun, Jun 15, 2025 at 10:12:18PM +0200, Ivan Vecera wrote:
> Enumerate all available DPLL channels and registers a DPLL device for
> each of them. Check all input references and outputs and register
> DPLL pins for them.
> 
> Number of registered DPLL pins depends on configuration of references
> and outputs. If the reference or output is configured as differential
> one then only one DPLL pin is registered. Both references and outputs
> can be also disabled from firmware configuration and in this case
> no DPLL pins are registered.
> 
> All registrable references are registered to all available DPLL devices
> with exception of DPLLs that are configured in NCO (numerically
> controlled oscillator) mode. In this mode DPLL channel acts as PHC and
> cannot be locked to any reference.
> 
> Device outputs are connected to one of synthesizers and each synthesizer
> is driven by some DPLL channel. So output pins belonging to given output
> are registered to DPLL device that drives associated synthesizer.
> 
> Finally add kworker task to monitor async changes on all DPLL channels
> and input pins and to notify about them DPLL core. Output pins are not
> monitored as their parameters are not changed asynchronously by the
> device.
> 
> Co-developed-by: Prathosh Satish <Prathosh.Satish@microchip.com>
> Signed-off-by: Prathosh Satish <Prathosh.Satish@microchip.com>
> Signed-off-by: Ivan Vecera <ivecera@redhat.com>

...

> diff --git a/drivers/dpll/zl3073x/core.c b/drivers/dpll/zl3073x/core.c

...

> +static int
> +zl3073x_devm_dpll_init(struct zl3073x_dev *zldev, u8 num_dplls)
> +{
> +	struct kthread_worker *kworker;
> +	struct zl3073x_dpll *zldpll;
> +	unsigned int i;
> +	int rc;
> +
> +	INIT_LIST_HEAD(&zldev->dplls);
> +
> +	/* Initialize all DPLLs */
> +	for (i = 0; i < num_dplls; i++) {
> +		zldpll = zl3073x_dpll_alloc(zldev, i);
> +		if (IS_ERR(zldpll)) {
> +			dev_err_probe(zldev->dev, PTR_ERR(zldpll),
> +				      "Failed to alloc DPLL%u\n", i);

Hi Ivan,

Jumping to the error label will return rc.
But rc may not be initialised here.

Flagged by Smatch.

> +			goto error;
> +		}
> +
> +		rc = zl3073x_dpll_register(zldpll);
> +		if (rc) {
> +			dev_err_probe(zldev->dev, rc,
> +				      "Failed to register DPLL%u\n", i);
> +			zl3073x_dpll_free(zldpll);
> +			goto error;
> +		}
> +
> +		list_add(&zldpll->list, &zldev->dplls);
> +	}
> +
> +	/* Perform initial firmware fine phase correction */
> +	rc = zl3073x_dpll_init_fine_phase_adjust(zldev);
> +	if (rc) {
> +		dev_err_probe(zldev->dev, rc,
> +			      "Failed to init fine phase correction\n");
> +		goto error;
> +	}
> +
> +	/* Initialize monitoring thread */
> +	kthread_init_delayed_work(&zldev->work, zl3073x_dev_periodic_work);
> +	kworker = kthread_run_worker(0, "zl3073x-%s", dev_name(zldev->dev));
> +	if (IS_ERR(kworker)) {
> +		rc = PTR_ERR(kworker);
> +		goto error;
> +	}
> +
> +	zldev->kworker = kworker;
> +	kthread_queue_delayed_work(zldev->kworker, &zldev->work, 0);
> +
> +	/* Add devres action to release DPLL related resources */
> +	rc = devm_add_action_or_reset(zldev->dev, zl3073x_dev_dpll_fini, zldev);
> +	if (rc)
> +		goto error;
> +
> +	return 0;
> +
> +error:
> +	zl3073x_dev_dpll_fini(zldev);
> +
> +	return rc;
> +}
> +

...

-- 
pw-bot: cr

  reply	other threads:[~2025-06-16 16:00 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-15 20:12 [PATCH net-next v10 00/14] Add Microchip ZL3073x support (part 1) Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 01/14] dt-bindings: dpll: Add DPLL device and pin Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 02/14] dt-bindings: dpll: Add support for Microchip Azurite chip family Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 03/14] dpll: Add basic Microchip ZL3073x support Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 04/14] dpll: zl3073x: Add support for devlink device info Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 05/14] dpll: zl3073x: Protect operations requiring multiple register accesses Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 06/14] dpll: zl3073x: Fetch invariants during probe Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 07/14] dpll: zl3073x: Add clock_id field Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 08/14] dpll: zl3073x: Read DPLL types and pin properties from system firmware Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 09/14] dpll: zl3073x: Register DPLL devices and pins Ivan Vecera
2025-06-16 16:00   ` Simon Horman [this message]
2025-06-16 16:40     ` Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 10/14] dpll: zl3073x: Implement input pin selection in manual mode Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 11/14] dpll: zl3073x: Add support to get/set priority on input pins Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 12/14] dpll: zl3073x: Implement input pin state setting in automatic mode Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 13/14] dpll: zl3073x: Add support to get/set frequency on input pins Ivan Vecera
2025-06-15 20:12 ` [PATCH net-next v10 14/14] dpll: zl3073x: Add support to get/set frequency on output pins Ivan Vecera

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