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From: Robert Cross <quantumcross@gmail.com>
To: andrew@lunn.ch
Cc: bpf@vger.kernel.org, davem@davemloft.net, edumazet@google.com,
	kuba@kernel.org, linux-kernel@vger.kernel.org,
	netdev@vger.kernel.org, olteanv@gmail.com, pabeni@redhat.com,
	quantumcross@gmail.com
Subject: Re: [PATCH v2] net: dsa: mv88e6xxx: fix external smi for mv88e6176
Date: Mon, 16 Jun 2025 15:12:14 -0400	[thread overview]
Message-ID: <20250616191214.2295467-1-quantumcross@gmail.com> (raw)
In-Reply-To: <ad17b701-f260-473f-b96f-0668ce052e75@lunn.ch>

> The MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL bit is reserved on the 6352
> family.

Indeed it is...

> You are not understanding what i'm saying. This family has a single
> MDIO bus controller. That controller is used by both the internal PHY
> devices, plus there are two pins on the chip for external PHYs.
>
> All the PHYs will appear on that one MDIO bus controller.

So you're saying that if I removed my hack that apparently just sets
this reserved bit, and I take my PHY on port 6 and remove it from
the mdio_ext { compatible = "marvell,mv88e6xxx-mdio-external"; } entry
and put it in my mdio { } node it will direct requests to address 6 to
the external phy via the MDC/MDIO_PHY pins just fine?

I'm guessing it will just automatically enable or disable the external
SMI pins depending on the state of port 5 which shares pins?

I'm also guessing that ports 0, 1, 2, 3, and 4 will map to the
internal PHYs (because there are 5) and then ports 5 and 6
automagically externally...

I shudder to think how by what forbidden voodoo my current device
tree actually works with this hack...

Thank you so much for your explanation. Hopefully I'll have a
real substantive patch in the future :)

  reply	other threads:[~2025-06-16 19:12 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-16 16:20 [PATCH v2] net: dsa: mv88e6xxx: fix external smi for mv88e6176 Robert Cross
2025-06-16 17:55 ` Andrew Lunn
2025-06-16 18:22   ` Robert Cross
2025-06-16 18:43     ` Andrew Lunn
2025-06-16 19:12       ` Robert Cross [this message]
2025-06-16 19:20         ` Andrew Lunn
2025-06-16 20:43       ` Robert Cross
2025-06-16 20:52       ` Vladimir Oltean
2025-06-16 21:18         ` Andrew Lunn

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