From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C786325291B; Mon, 23 Jun 2025 10:30:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750674651; cv=none; b=p8Yr/sMpHSgf7JJrhY+8BHsXVEoZ59L3rJYmCul8xhIOIvhbHCFYkWco3qDpAhmvc1+U2N58R+pDCbWQ20d0h9Yw1AA0CjEi9Ah4MdhZogIAtukDhNgQNodqXv2834yY2qEOBw0v+p6m2JTA4U+wgoHMh6Vbmh2FBMGObaZlkmU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750674651; c=relaxed/simple; bh=WPbiKU4UmisefgWlCdumuilVqbKg0Ayb/7S0PUCT5Bs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GfTt4JM0cLGZb6SUMUF+eEM4ur55dli76dAQJp/KtpKGQ5MeritqzgwvPsCyxNXPt1fHWduUiCZBNrUyUtbTFV+LLoqs8qpprcyTk4tiyKwd6t7VNET5dHhzRCq16YBbch/rtRclcMNeMbI2Juii+FUPlG2H0DWX2WUld7NOVeg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=jTM+ApzD; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="jTM+ApzD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750674647; bh=WPbiKU4UmisefgWlCdumuilVqbKg0Ayb/7S0PUCT5Bs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jTM+ApzDwLMEEfu6DsS1CwLDy+NPnpdQny9FJ6RRtq/MW0JpQ4AdIkagW13QtHlXd PMp/wYQBLvG/lgSJ2WsyLBabpJni+K6RXd5J0ZzWjB7cU/zSM5+FryvC+T0Llhl61Z ii68YNy3hYOcIp37J7gPLlVRj7z1RN3NLVrWlPlOQFnv346/RCXwNEqWL49lCpbew3 T/qbTABK2cJKwouTdVefOuXjTIfK4V+Q4N8wdPD5KXT1LL4xVZudKf1f9bZiMUv4wJ Sg5Sanmgh5SzHglpyLM5CRccMNpkAz6xHUNNke1jq1hLveyie6NSYHXQLSkGi7yDR2 QsxuTI0pfBIGw== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:e046:b666:1d47:e832]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4006917E05BD; Mon, 23 Jun 2025 12:30:46 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao Subject: [PATCH 16/30] clk: mediatek: Add MT8196 pextpsys clock support Date: Mon, 23 Jun 2025 12:29:26 +0200 Message-Id: <20250623102940.214269-17-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250623102940.214269-1-laura.nao@collabora.com> References: <20250623102940.214269-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add support for the MT8196 pextpsys clock controller, which provides clock gate control for PCIe. Signed-off-by: Laura Nao --- drivers/clk/mediatek/Kconfig | 7 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8196-pextp.c | 95 +++++++++++++++++++++++++ 3 files changed, 103 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8196-pextp.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 848624792a23..cd12e7ff3e12 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -1068,6 +1068,13 @@ config COMMON_CLK_MT8196 help This driver supports MediaTek MT8196 basic clocks. +config COMMON_CLK_MT8196_PEXTPSYS + tristate "Clock driver for MediaTek MT8196 pextpsys" + depends on COMMON_CLK_MT8196 + default COMMON_CLK_MT8196 + help + This driver supports MediaTek MT8196 pextpsys clocks. + config COMMON_CLK_MT8196_UFSSYS tristate "Clock driver for MediaTek MT8196 ufssys" depends on COMMON_CLK_MT8196 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index ee6a1bb5ce38..21e768f67283 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -163,6 +163,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o \ clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \ clk-mt8196-peri_ao.o +obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o diff --git a/drivers/clk/mediatek/clk-mt8196-pextp.c b/drivers/clk/mediatek/clk-mt8196-pextp.c new file mode 100644 index 000000000000..938100e4836b --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8196-pextp.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + * Guangjie Song + * Copyright (c) 2025 Collabora Ltd. + * Laura Nao + */ +#include +#include +#include +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs pext_cg_regs = { + .set_ofs = 0x18, + .clr_ofs = 0x1c, + .sta_ofs = 0x14, +}; + +#define GATE_PEXT(_id, _name, _parent, _shift) {\ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &pext_cg_regs, \ + .shift = _shift, \ + .flags = CLK_OPS_PARENT_ENABLE, \ + .ops = &mtk_clk_gate_ops_setclr,\ + } + +static const struct mtk_gate pext_clks[] = { + GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_TL, "pext_pm0_tl", "tl", 0), + GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_REF, "pext_pm0_ref", "clk26m", 1), + GATE_PEXT(CLK_PEXT_PEXTP_PHY_P0_MCU_BUS, "pext_pp0_mcu_bus", "clk26m", 6), + GATE_PEXT(CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF, "pext_pp0_pextp_ref", "clk26m", 7), + GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_AXI_250, "pext_pm0_axi_250", "ufs_pexpt0_mem_sub", 12), + GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_AHB_APB, "pext_pm0_ahb_apb", "ufs_pextp0_axi", 13), + GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_PL_P, "pext_pm0_pl_p", "clk26m", 14), + GATE_PEXT(CLK_PEXT_PEXTP_VLP_AO_P0_LP, "pext_pextp_vlp_ao_p0_lp", "clk26m", 19), +}; + +static const struct mtk_clk_desc pext_mcd = { + .clks = pext_clks, + .num_clks = ARRAY_SIZE(pext_clks), +}; + +static const struct mtk_gate pext1_clks[] = { + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_TL, "pext1_pm1_tl", "tl_p1", 0), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_REF, "pext1_pm1_ref", "clk26m", 1), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_TL, "pext1_pm2_tl", "tl_p2", 2), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_REF, "pext1_pm2_ref", "clk26m", 3), + GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS, "pext1_pp1_mcu_bus", "clk26m", 8), + GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF, "pext1_pp1_pextp_ref", "clk26m", 9), + GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS, "pext1_pp2_mcu_bus", "clk26m", 10), + GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF, "pext1_pp2_pextp_ref", "clk26m", 11), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_AXI_250, "pext1_pm1_axi_250", + "pextp1_usb_axi", 16), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_AHB_APB, "pext1_pm1_ahb_apb", + "pextp1_usb_mem_sub", 17), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_PL_P, "pext1_pm1_pl_p", "clk26m", 18), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_AXI_250, "pext1_pm2_axi_250", + "pextp1_usb_axi", 19), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_AHB_APB, "pext1_pm2_ahb_apb", + "pextp1_usb_mem_sub", 20), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_PL_P, "pext1_pm2_pl_p", "clk26m", 21), + GATE_PEXT(CLK_PEXT1_PEXTP_VLP_AO_P1_LP, "pext1_pextp_vlp_ao_p1_lp", "clk26m", 26), + GATE_PEXT(CLK_PEXT1_PEXTP_VLP_AO_P2_LP, "pext1_pextp_vlp_ao_p2_lp", "clk26m", 27), +}; + +static const struct mtk_clk_desc pext1_mcd = { + .clks = pext1_clks, + .num_clks = ARRAY_SIZE(pext1_clks), +}; + +static const struct of_device_id of_match_clk_mt8196_pextp[] = { + { .compatible = "mediatek,mt8196-pextp0cfg-ao", .data = &pext_mcd }, + { .compatible = "mediatek,mt8196-pextp1cfg-ao", .data = &pext1_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_pextp); + +static struct platform_driver clk_mt8196_pextp_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8196-pextp", + .of_match_table = of_match_clk_mt8196_pextp, + }, +}; + +module_platform_driver(clk_mt8196_pextp_drv); +MODULE_DESCRIPTION("MediaTek MT8196 PCIe transmit phy clocks driver"); +MODULE_LICENSE("GPL"); -- 2.39.5