From: kernel test robot <lkp@intel.com>
To: Laura Nao <laura.nao@collabora.com>,
mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com,
angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de,
richardcochran@gmail.com
Cc: oe-kbuild-all@lists.linux.dev, guangjie.song@mediatek.com,
wenst@chromium.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
kernel@collabora.com, Laura Nao <laura.nao@collabora.com>
Subject: Re: [PATCH 24/30] clk: mediatek: Add MT8196 disp-ao clock support
Date: Tue, 24 Jun 2025 14:40:55 +0800 [thread overview]
Message-ID: <202506241439.PGytyi4q-lkp@intel.com> (raw)
In-Reply-To: <20250623102940.214269-25-laura.nao@collabora.com>
Hi Laura,
kernel test robot noticed the following build warnings:
[auto build test WARNING on clk/clk-next]
[also build test WARNING on linus/master v6.16-rc3 next-20250623]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Laura-Nao/clk-mediatek-clk-pll-Add-set-clr-regs-for-shared-PLL-enable-control/20250623-184204
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link: https://lore.kernel.org/r/20250623102940.214269-25-laura.nao%40collabora.com
patch subject: [PATCH 24/30] clk: mediatek: Add MT8196 disp-ao clock support
config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20250624/202506241439.PGytyi4q-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250624/202506241439.PGytyi4q-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202506241439.PGytyi4q-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/clk/mediatek/clk-mt8196-vdisp_ao.c:62:34: warning: 'of_match_clk_mt8196_vdisp_ao' defined but not used [-Wunused-const-variable=]
62 | static const struct of_device_id of_match_clk_mt8196_vdisp_ao[] = {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/of_match_clk_mt8196_vdisp_ao +62 drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
61
> 62 static const struct of_device_id of_match_clk_mt8196_vdisp_ao[] = {
63 { .compatible = "mediatek,mt8196-vdisp-ao", .data = &mm_v_mcd },
64 { /* sentinel */ }
65 };
66 MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_vdisp_ao);
67
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next prev parent reply other threads:[~2025-06-24 6:41 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-23 10:29 [PATCH 00/30] Add support for MT8196 clock controllers Laura Nao
2025-06-23 10:29 ` [PATCH 01/30] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-06-23 10:29 ` [PATCH 02/30] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-06-23 10:29 ` [PATCH 03/30] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-06-23 10:29 ` [PATCH 04/30] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-06-23 10:29 ` [PATCH 05/30] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-06-23 10:29 ` [PATCH 06/30] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-06-23 10:29 ` [PATCH 07/30] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-06-23 10:29 ` [PATCH 08/30] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-06-23 10:29 ` [PATCH 09/30] dt-bindings: clock: mediatek: Describe MT8196 peripheral clock controllers Laura Nao
2025-06-23 12:12 ` Krzysztof Kozlowski
2025-06-23 12:28 ` AngeloGioacchino Del Regno
2025-06-23 10:29 ` [PATCH 10/30] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-06-23 10:29 ` [PATCH 11/30] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-06-23 10:29 ` [PATCH 12/30] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-06-23 10:29 ` [PATCH 13/30] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-06-23 10:29 ` [PATCH 14/30] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-06-23 10:29 ` [PATCH 15/30] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-06-23 10:29 ` [PATCH 16/30] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-06-23 10:29 ` [PATCH 17/30] clk: mediatek: Add MT8196 adsp " Laura Nao
2025-06-23 10:29 ` [PATCH 18/30] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-06-23 10:29 ` [PATCH 19/30] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-06-23 10:29 ` [PATCH 20/30] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-06-23 10:29 ` [PATCH 21/30] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-06-23 10:29 ` [PATCH 22/30] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-06-23 10:29 ` [PATCH 23/30] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-06-23 10:29 ` [PATCH 24/30] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2025-06-24 6:40 ` kernel test robot [this message]
2025-06-23 10:29 ` [PATCH 25/30] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-06-23 10:29 ` [PATCH 26/30] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-06-23 10:29 ` [PATCH 27/30] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-06-23 10:29 ` [PATCH 28/30] clk: mediatek: Add MT8196 vencsys " Laura Nao
2025-06-23 10:29 ` [PATCH 29/30] dt-bindings: reset: Add MediaTek MT8196 Reset Controller binding Laura Nao
2025-06-23 12:13 ` Krzysztof Kozlowski
2025-06-23 12:22 ` AngeloGioacchino Del Regno
2025-06-23 10:29 ` [PATCH 30/30] clk: mediatek: mt8196: Add UFS and PEXTP0/1 reset controllers Laura Nao
2025-06-23 12:14 ` Krzysztof Kozlowski
2025-06-23 12:33 ` AngeloGioacchino Del Regno
2025-06-23 11:34 ` [PATCH 00/30] Add support for MT8196 clock controllers AngeloGioacchino Del Regno
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