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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 10:12:33.6274 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60a6a05c-7ea0-4bce-9950-08ddbf9a4997 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5889 AXI ethernet driver uses AXI DMA dmaengine driver. Add support to configure / report coalesce parameters dynamically during runtime via ethtool. Add support in DMAengine driver to communicate coalesce parameters between client and DMA driver. Add support for Tx and Rx adaptive irq coalescing with DIM in AXI ethernet driver. Changes in V2: - Add DIM in AXI ethernet driver. - Fix following LKP warning in V1: https://lore.kernel.org/all/202505252153.Nm1BzFUq-lkp@intel.com/ - Consolidate separate Dmaengine and netdev series in V1. V1 axienet and dmaengine series: https://lore.kernel.org/all/20250525101617.1168991-1-suraj.gupta2@amd.com/ https://lore.kernel.org/all/20250525102217.1181104-1-suraj.gupta2@amd.com/ Suraj Gupta (4): dmaengine: Add support to configure and read IRQ coalescing parameters dmaengine: xilinx_dma: Fix irq handler and start transfer path for AXI DMA dmaengine: xilinx_dma: Add support to configure/report coalesce parameters from/to client using AXI DMA net: xilinx: axienet: Add ethtool support to configure/report irq coalescing parameters in DMAengine flow drivers/dma/xilinx/xilinx_dma.c | 93 +++++++-- drivers/net/ethernet/xilinx/xilinx_axienet.h | 13 +- .../net/ethernet/xilinx/xilinx_axienet_main.c | 190 +++++++++++++++++- include/linux/dmaengine.h | 10 + 4 files changed, 276 insertions(+), 30 deletions(-) -- 2.25.1