From: Jack Ping CHNG <jchng@maxlinear.com>
To: <netdev@vger.kernel.org>
Cc: <davem@davemloft.net>, <fancer.lancer@gmail.com>,
<yzhu@maxlinear.com>, <sureshnagaraj@maxlinear.com>,
Jack Ping CHNG <jchng@maxlinear.com>
Subject: [PATCH net-next] net: pcs: xpcs: mask readl() return value to 16 bits
Date: Wed, 16 Jul 2025 11:03:49 +0800 [thread overview]
Message-ID: <20250716030349.3796806-1-jchng@maxlinear.com> (raw)
readl() returns 32-bit value but Clause 22/45 registers are 16-bit wide.
Masking with 0xFFFF avoids using garbage upper bits.
Signed-off-by: Jack Ping CHNG <jchng@maxlinear.com>
---
drivers/net/pcs/pcs-xpcs-plat.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/pcs/pcs-xpcs-plat.c b/drivers/net/pcs/pcs-xpcs-plat.c
index 629315f1e57c..9dcaf7a66113 100644
--- a/drivers/net/pcs/pcs-xpcs-plat.c
+++ b/drivers/net/pcs/pcs-xpcs-plat.c
@@ -66,7 +66,7 @@ static int xpcs_mmio_read_reg_indirect(struct dw_xpcs_plat *pxpcs,
switch (pxpcs->reg_width) {
case 4:
writel(page, pxpcs->reg_base + (DW_VR_CSR_VIEWPORT << 2));
- ret = readl(pxpcs->reg_base + (ofs << 2));
+ ret = readl(pxpcs->reg_base + (ofs << 2)) & 0xffff;
break;
default:
writew(page, pxpcs->reg_base + (DW_VR_CSR_VIEWPORT << 1));
@@ -124,7 +124,7 @@ static int xpcs_mmio_read_reg_direct(struct dw_xpcs_plat *pxpcs,
switch (pxpcs->reg_width) {
case 4:
- ret = readl(pxpcs->reg_base + (csr << 2));
+ ret = readl(pxpcs->reg_base + (csr << 2)) & 0xffff;
break;
default:
ret = readw(pxpcs->reg_base + (csr << 1));
--
2.43.0
next reply other threads:[~2025-07-16 3:03 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-16 3:03 Jack Ping CHNG [this message]
2025-07-16 7:25 ` [PATCH net-next] net: pcs: xpcs: mask readl() return value to 16 bits Maxime Chevallier
2025-07-16 8:00 ` Jack Ping Chng
2025-07-18 2:00 ` patchwork-bot+netdevbpf
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