Re: [PATCH net-next 1/5] net: dsa: mv88e6xxx: rename TAI definitions according to core

[Vladimir Oltean <olteanv@gmail.com>]

On Tue, Sep 16, 2025 at 02:36:00PM +0100, Russell King (Oracle) wrote:
> On Tue, Sep 16, 2025 at 11:46:45AM +0300, Vladimir Oltean wrote:
> > On Mon, Sep 15, 2025 at 02:06:15PM +0100, Russell King (Oracle) wrote:
> > >  /* Offset 0x09: Event Status */
> > > -#define MV88E6XXX_TAI_EVENT_STATUS		0x09
> > > -#define MV88E6XXX_TAI_EVENT_STATUS_ERROR	0x0200
> > > -#define MV88E6XXX_TAI_EVENT_STATUS_VALID	0x0100
> > > -#define MV88E6XXX_TAI_EVENT_STATUS_CTR_MASK	0x00ff
> > > -
> > >  /* Offset 0x0A/0x0B: Event Time */
> > 
> > Was it intentional to keep the comment for a register with removed
> > definitions, and this placement for it? It looks like this (confusing
> > to me):
> > 
> > /* Offset 0x09: Event Status */
> > /* Offset 0x0A/0x0B: Event Time */
> > #define MV88E6352_TAI_EVENT_STATUS		0x09
> 
> Yes, totally intentional.
> 
> All three registers are read by the code - as a single block, rather
> than individually. While the definitions for the event time are not
> referenced, I wanted to keep their comment, and that seemed to be
> the most logical way.

What I don't find so logical is that the bit fields of MV88E6352_TAI_EVENT_STATUS
follow a comment which refers to "Event Time".

Do we read the registers in a single mv88e6xxx_tai_read() call because
the hardware requires us, or because of convenience? For writes, we
write only a single u16 corresponding to the Event Status, so I suspect
they are not completely indivisible, but I don't have documentation to
confirm.

This is more of what I was expecting.

/* Offset 0x09: Event Status */
#define MV88E6352_TAI_EVENT_STATUS		0x09
#define MV88E6352_TAI_EVENT_STATUS_CAP_TRIG	0x4000
#define MV88E6352_TAI_EVENT_STATUS_ERROR	0x0200
#define MV88E6352_TAI_EVENT_STATUS_VALID	0x0100
#define MV88E6352_TAI_EVENT_STATUS_CTR_MASK	0x00ff
/* Offset 0x0A/0x0B: Event Time Lo/Hi. Always read together with Event Status */

Anyway, this is not so important.