[PATCH mlx5-next 0/3] mlx5-next updates 2025-09-11

[PATCH mlx5-next 0/3] mlx5-next updates 2025-09-11

[Tariq Toukan]

Hi,

This series by Carolina contains cleanups significantly touching shared
mlx5 net and rdma headers.

Regards,
Tariq

Carolina Jubran (3):
  net/mlx5: Remove VLAN insertion fields from WQE Ether segment
  net/mlx5: Refactor MACsec WQE metadata shifts
  net/mlx5e: Prevent WQE metadata conflicts between timestamping and
    offloads

 .../mellanox/mlx5/core/en_accel/macsec.c         |  2 +-
 drivers/net/ethernet/mellanox/mlx5/core/en_tx.c  |  2 +-
 .../ethernet/mellanox/mlx5/core/lib/macsec_fs.c  | 14 ++++++--------
 .../ethernet/mellanox/mlx5/core/lib/macsec_fs.h  | 15 +++++++++++++++
 include/linux/mlx5/qp.h                          | 16 ++++++++--------
 5 files changed, 31 insertions(+), 18 deletions(-)


base-commit: ff97bc38be343e4530e2f140b40cbdce2e09152f
-- 
2.31.1

[PATCH mlx5-next 1/3] net/mlx5: Remove VLAN insertion fields from WQE Ether segment

[Tariq Toukan]

From: Carolina Jubran <cjubran@nvidia.com>

Now that the driver no longer uses VLAN TX insertion via the WQE
Ethernet segment, the related fields and flags can be removed.

Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
---
 include/linux/mlx5/qp.h | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h
index fc7eeff99a8a..5546c7bd2c83 100644
--- a/include/linux/mlx5/qp.h
+++ b/include/linux/mlx5/qp.h
@@ -237,13 +237,11 @@ enum {
 };
 
 enum {
-	MLX5_ETH_WQE_SVLAN              = 1 << 0,
 	MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC = 1 << 26,
 	MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC = 1 << 27,
 	MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC = 3 << 26,
 	MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC = 1 << 28,
 	MLX5_ETH_WQE_INSERT_TRAILER     = 1 << 30,
-	MLX5_ETH_WQE_INSERT_VLAN        = 1 << 15,
 };
 
 enum {
@@ -275,10 +273,6 @@ struct mlx5_wqe_eth_seg {
 				DECLARE_FLEX_ARRAY(u8, data);
 			};
 		} inline_hdr;
-		struct {
-			__be16 type;
-			__be16 vlan_tci;
-		} insert;
 		__be32 trailer;
 	};
 };
-- 
2.31.1

Re: [PATCH mlx5-next 1/3] net/mlx5: Remove VLAN insertion fields from WQE Ether segment

[Simon Horman]

On Thu, Sep 11, 2025 at 10:10:17AM +0300, Tariq Toukan wrote:
> From: Carolina Jubran <cjubran@nvidia.com>
> 
> Now that the driver no longer uses VLAN TX insertion via the WQE
> Ethernet segment, the related fields and flags can be removed.
> 
> Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
> Signed-off-by: Tariq Toukan <tariqt@nvidia.com>

Reviewed-by: Simon Horman <horms@kernel.org>

[PATCH mlx5-next 2/3] net/mlx5: Refactor MACsec WQE metadata shifts

[Tariq Toukan]

From: Carolina Jubran <cjubran@nvidia.com>

Introduce MLX5_ETH_WQE_FT_META_SHIFT as a shared base offset for
features that use the lower 8 bits of the WQE flow_table_metadata
field, currently used for timestamping, IPsec, and MACsec.

Define MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK so that fs_id occupies
bits 2–5, making it clear that fs_id occupies bits in the metadata.

Set MLX5_ETH_WQE_FT_META_MACSEC_MASK as the OR of the MACsec flag and
MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK, corresponding to the original
0x3E mask.

Update the fs_id macro to right-shift the MACsec flag by
MLX5_ETH_WQE_FT_META_SHIFT and update the RoCE modify-header action to
use it.

Introduce the helper macro MLX5_MACSEC_TX_METADATA(fs_id) to compose
the full shifted MACsec metadata value.

These changes make it explicit exactly which metadata bits carry MACsec
information, simplifying future feature exclusions when multiple
features share the WQE flowtable metadata.

In addition, drop the incorrect “RX flow steering” comment, since this
applies to TX flow steering.

Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Jianbo Liu <jianbol@nvidia.com>
Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
---
 .../ethernet/mellanox/mlx5/core/en_accel/macsec.c |  2 +-
 .../ethernet/mellanox/mlx5/core/lib/macsec_fs.c   | 12 +++++-------
 .../ethernet/mellanox/mlx5/core/lib/macsec_fs.h   | 15 +++++++++++++++
 include/linux/mlx5/qp.h                           |  9 +++++++--
 4 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c
index 6ab02f3fc291..528b04d4de41 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c
@@ -1676,7 +1676,7 @@ void mlx5e_macsec_tx_build_eseg(struct mlx5e_macsec *macsec,
 	if (!fs_id)
 		return;
 
-	eseg->flow_table_metadata = cpu_to_be32(MLX5_ETH_WQE_FT_META_MACSEC | fs_id << 2);
+	eseg->flow_table_metadata = cpu_to_be32(MLX5_MACSEC_TX_METADATA(fs_id));
 }
 
 void mlx5e_macsec_offload_handle_rx_skb(struct net_device *netdev,
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c
index 762d55ba9e51..9ec450603176 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c
@@ -45,11 +45,7 @@
 #define MLX5_SECTAG_HEADER_SIZE_WITHOUT_SCI 0x8
 #define MLX5_SECTAG_HEADER_SIZE_WITH_SCI (MLX5_SECTAG_HEADER_SIZE_WITHOUT_SCI + MACSEC_SCI_LEN)
 
-/* MACsec RX flow steering */
-#define MLX5_ETH_WQE_FT_META_MACSEC_MASK 0x3E
-
 /* MACsec fs_id handling for steering */
-#define macsec_fs_set_tx_fs_id(fs_id) (MLX5_ETH_WQE_FT_META_MACSEC | (fs_id) << 2)
 #define macsec_fs_set_rx_fs_id(fs_id) ((fs_id) | BIT(30))
 
 struct mlx5_sectag_header {
@@ -597,7 +593,7 @@ static int macsec_fs_tx_setup_fte(struct mlx5_macsec_fs *macsec_fs,
 	MLX5_SET(fte_match_param, spec->match_criteria, misc_parameters_2.metadata_reg_a,
 		 MLX5_ETH_WQE_FT_META_MACSEC_MASK);
 	MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_a,
-		 macsec_fs_set_tx_fs_id(id));
+		 MLX5_MACSEC_TX_METADATA(id));
 
 	*fs_id = id;
 	flow_act->crypto.type = MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC;
@@ -2219,8 +2215,10 @@ static int mlx5_macsec_fs_add_roce_rule_tx(struct mlx5_macsec_fs *macsec_fs, u32
 
 	MLX5_SET(set_action_in, action, action_type, MLX5_ACTION_TYPE_SET);
 	MLX5_SET(set_action_in, action, field, MLX5_ACTION_IN_FIELD_METADATA_REG_A);
-	MLX5_SET(set_action_in, action, data, macsec_fs_set_tx_fs_id(fs_id));
-	MLX5_SET(set_action_in, action, offset, 0);
+	MLX5_SET(set_action_in, action, data,
+		 mlx5_macsec_fs_set_tx_fs_id(fs_id));
+	MLX5_SET(set_action_in, action, offset,
+		 MLX5_ETH_WQE_FT_META_MACSEC_SHIFT);
 	MLX5_SET(set_action_in, action, length, 32);
 
 	modify_hdr = mlx5_modify_header_alloc(mdev, MLX5_FLOW_NAMESPACE_RDMA_TX_MACSEC,
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h
index 34b80c3ef6a5..15acaff43641 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h
@@ -12,6 +12,21 @@
 #define MLX5_MACSEC_METADATA_MARKER(metadata)  ((((metadata) >> 30) & 0x3)  == 0x1)
 #define MLX5_MACSEC_RX_METADAT_HANDLE(metadata)  ((metadata) & MLX5_MACSEC_RX_FS_ID_MASK)
 
+/* MACsec TX flow steering */
+#define MLX5_ETH_WQE_FT_META_MACSEC_MASK \
+	(MLX5_ETH_WQE_FT_META_MACSEC | MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK)
+#define MLX5_ETH_WQE_FT_META_MACSEC_SHIFT MLX5_ETH_WQE_FT_META_SHIFT
+
+/* MACsec fs_id handling for steering */
+#define mlx5_macsec_fs_set_tx_fs_id(fs_id) \
+	(((MLX5_ETH_WQE_FT_META_MACSEC) >> MLX5_ETH_WQE_FT_META_MACSEC_SHIFT) \
+	 | ((fs_id) << 2))
+
+#define MLX5_MACSEC_TX_METADATA(fs_id) \
+	(mlx5_macsec_fs_set_tx_fs_id(fs_id) << \
+	 MLX5_ETH_WQE_FT_META_MACSEC_SHIFT)
+
+/* MACsec fs_id uses 4 bits, supports up to 16 interfaces */
 #define MLX5_MACSEC_NUM_OF_SUPPORTED_INTERFACES 16
 
 struct mlx5_macsec_fs;
diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h
index 5546c7bd2c83..b21be7630575 100644
--- a/include/linux/mlx5/qp.h
+++ b/include/linux/mlx5/qp.h
@@ -251,9 +251,14 @@ enum {
 	MLX5_ETH_WQE_SWP_OUTER_L4_UDP   = 1 << 5,
 };
 
+/* Base shift for metadata bits used by timestamping, IPsec, and MACsec */
+#define MLX5_ETH_WQE_FT_META_SHIFT 0
+
 enum {
-	MLX5_ETH_WQE_FT_META_IPSEC = BIT(0),
-	MLX5_ETH_WQE_FT_META_MACSEC = BIT(1),
+	MLX5_ETH_WQE_FT_META_IPSEC = BIT(0) << MLX5_ETH_WQE_FT_META_SHIFT,
+	MLX5_ETH_WQE_FT_META_MACSEC = BIT(1) << MLX5_ETH_WQE_FT_META_SHIFT,
+	MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK =
+		GENMASK(5, 2) << MLX5_ETH_WQE_FT_META_SHIFT,
 };
 
 struct mlx5_wqe_eth_seg {
-- 
2.31.1

Re: [PATCH mlx5-next 2/3] net/mlx5: Refactor MACsec WQE metadata shifts

[Simon Horman]

On Thu, Sep 11, 2025 at 10:10:18AM +0300, Tariq Toukan wrote:
> From: Carolina Jubran <cjubran@nvidia.com>
> 
> Introduce MLX5_ETH_WQE_FT_META_SHIFT as a shared base offset for
> features that use the lower 8 bits of the WQE flow_table_metadata
> field, currently used for timestamping, IPsec, and MACsec.
> 
> Define MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK so that fs_id occupies
> bits 2–5, making it clear that fs_id occupies bits in the metadata.
> 
> Set MLX5_ETH_WQE_FT_META_MACSEC_MASK as the OR of the MACsec flag and
> MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK, corresponding to the original
> 0x3E mask.
> 
> Update the fs_id macro to right-shift the MACsec flag by
> MLX5_ETH_WQE_FT_META_SHIFT and update the RoCE modify-header action to
> use it.
> 
> Introduce the helper macro MLX5_MACSEC_TX_METADATA(fs_id) to compose
> the full shifted MACsec metadata value.
> 
> These changes make it explicit exactly which metadata bits carry MACsec
> information, simplifying future feature exclusions when multiple
> features share the WQE flowtable metadata.
> 
> In addition, drop the incorrect “RX flow steering” comment, since this
> applies to TX flow steering.
> 
> Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
> Reviewed-by: Jianbo Liu <jianbol@nvidia.com>
> Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
> Signed-off-by: Tariq Toukan <tariqt@nvidia.com>

Hi Carolina, Tariq, all,

I'm wondering if dropping _SHIFT and making use of FIELD_PREP
would lead to a cleaner and more idiomatic implementation.

I'm thinking that such an approach would involve
updating MLX5_ETH_WQE_FT_META_MACSEC_MASK rather
than MLX5_ETH_WQE_FT_META_MACSEC_SHIFT in the following patch.

I'm thinking of something along the lines of following incremental patch.

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c
index 9ec450603176..58c0ff4af78f 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c
@@ -2218,7 +2218,7 @@ static int mlx5_macsec_fs_add_roce_rule_tx(struct mlx5_macsec_fs *macsec_fs, u32
 	MLX5_SET(set_action_in, action, data,
 		 mlx5_macsec_fs_set_tx_fs_id(fs_id));
 	MLX5_SET(set_action_in, action, offset,
-		 MLX5_ETH_WQE_FT_META_MACSEC_SHIFT);
+		 __bf_shf(MLX5_ETH_WQE_FT_META_MACSEC_MASK));
 	MLX5_SET(set_action_in, action, length, 32);
 
 	modify_hdr = mlx5_modify_header_alloc(mdev, MLX5_FLOW_NAMESPACE_RDMA_TX_MACSEC,
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h
index 15acaff43641..402840cb3110 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h
@@ -13,18 +13,15 @@
 #define MLX5_MACSEC_RX_METADAT_HANDLE(metadata)  ((metadata) & MLX5_MACSEC_RX_FS_ID_MASK)
 
 /* MACsec TX flow steering */
-#define MLX5_ETH_WQE_FT_META_MACSEC_MASK \
-	(MLX5_ETH_WQE_FT_META_MACSEC | MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK)
-#define MLX5_ETH_WQE_FT_META_MACSEC_SHIFT MLX5_ETH_WQE_FT_META_SHIFT
+#define MLX5_ETH_WQE_FT_META_MACSEC_MASK GENMASK(7, 0)
 
 /* MACsec fs_id handling for steering */
 #define mlx5_macsec_fs_set_tx_fs_id(fs_id) \
-	(((MLX5_ETH_WQE_FT_META_MACSEC) >> MLX5_ETH_WQE_FT_META_MACSEC_SHIFT) \
-	 | ((fs_id) << 2))
+	(MLX5_ETH_WQE_FT_META_IPSEC | (fs_id) << 2)
 
 #define MLX5_MACSEC_TX_METADATA(fs_id) \
-	(mlx5_macsec_fs_set_tx_fs_id(fs_id) << \
-	 MLX5_ETH_WQE_FT_META_MACSEC_SHIFT)
+	FIELD_PREP(MLX5_ETH_WQE_FT_META_MACSEC_MASK, \
+		   mlx5_macsec_fs_set_tx_fs_id(fs_id))
 
 /* MACsec fs_id uses 4 bits, supports up to 16 interfaces */
 #define MLX5_MACSEC_NUM_OF_SUPPORTED_INTERFACES 16
diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h
index b21be7630575..5546c7bd2c83 100644
--- a/include/linux/mlx5/qp.h
+++ b/include/linux/mlx5/qp.h
@@ -251,14 +251,9 @@ enum {
 	MLX5_ETH_WQE_SWP_OUTER_L4_UDP   = 1 << 5,
 };
 
-/* Base shift for metadata bits used by timestamping, IPsec, and MACsec */
-#define MLX5_ETH_WQE_FT_META_SHIFT 0
-
 enum {
-	MLX5_ETH_WQE_FT_META_IPSEC = BIT(0) << MLX5_ETH_WQE_FT_META_SHIFT,
-	MLX5_ETH_WQE_FT_META_MACSEC = BIT(1) << MLX5_ETH_WQE_FT_META_SHIFT,
-	MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK =
-		GENMASK(5, 2) << MLX5_ETH_WQE_FT_META_SHIFT,
+	MLX5_ETH_WQE_FT_META_IPSEC = BIT(0),
+	MLX5_ETH_WQE_FT_META_MACSEC = BIT(1),
 };
 
 struct mlx5_wqe_eth_seg {

Re: [PATCH mlx5-next 2/3] net/mlx5: Refactor MACsec WQE metadata shifts

[Carolina Jubran]

On 12/09/2025 18:49, Simon Horman wrote:
> On Thu, Sep 11, 2025 at 10:10:18AM +0300, Tariq Toukan wrote:
>> From: Carolina Jubran <cjubran@nvidia.com>
>>
>> Introduce MLX5_ETH_WQE_FT_META_SHIFT as a shared base offset for
>> features that use the lower 8 bits of the WQE flow_table_metadata
>> field, currently used for timestamping, IPsec, and MACsec.
>>
>> Define MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK so that fs_id occupies
>> bits 2–5, making it clear that fs_id occupies bits in the metadata.
>>
>> Set MLX5_ETH_WQE_FT_META_MACSEC_MASK as the OR of the MACsec flag and
>> MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK, corresponding to the original
>> 0x3E mask.
>>
>> Update the fs_id macro to right-shift the MACsec flag by
>> MLX5_ETH_WQE_FT_META_SHIFT and update the RoCE modify-header action to
>> use it.
>>
>> Introduce the helper macro MLX5_MACSEC_TX_METADATA(fs_id) to compose
>> the full shifted MACsec metadata value.
>>
>> These changes make it explicit exactly which metadata bits carry MACsec
>> information, simplifying future feature exclusions when multiple
>> features share the WQE flowtable metadata.
>>
>> In addition, drop the incorrect “RX flow steering” comment, since this
>> applies to TX flow steering.
>>
>> Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
>> Reviewed-by: Jianbo Liu <jianbol@nvidia.com>
>> Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
>> Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
> Hi Carolina, Tariq, all,
>
> I'm wondering if dropping _SHIFT and making use of FIELD_PREP
> would lead to a cleaner and more idiomatic implementation.
>
> I'm thinking that such an approach would involve
> updating MLX5_ETH_WQE_FT_META_MACSEC_MASK rather
> than MLX5_ETH_WQE_FT_META_MACSEC_SHIFT in the following patch.
>
> I'm thinking of something along the lines of following incremental patch.
>
> diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c
> index 9ec450603176..58c0ff4af78f 100644
> --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c
> +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c
> @@ -2218,7 +2218,7 @@ static int mlx5_macsec_fs_add_roce_rule_tx(struct mlx5_macsec_fs *macsec_fs, u32
>   	MLX5_SET(set_action_in, action, data,
>   		 mlx5_macsec_fs_set_tx_fs_id(fs_id));
>   	MLX5_SET(set_action_in, action, offset,
> -		 MLX5_ETH_WQE_FT_META_MACSEC_SHIFT);
> +		 __bf_shf(MLX5_ETH_WQE_FT_META_MACSEC_MASK));
>   	MLX5_SET(set_action_in, action, length, 32);
>   
>   	modify_hdr = mlx5_modify_header_alloc(mdev, MLX5_FLOW_NAMESPACE_RDMA_TX_MACSEC,
> diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h
> index 15acaff43641..402840cb3110 100644
> --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h
> +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h
> @@ -13,18 +13,15 @@
>   #define MLX5_MACSEC_RX_METADAT_HANDLE(metadata)  ((metadata) & MLX5_MACSEC_RX_FS_ID_MASK)
>   
>   /* MACsec TX flow steering */
> -#define MLX5_ETH_WQE_FT_META_MACSEC_MASK \
> -	(MLX5_ETH_WQE_FT_META_MACSEC | MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK)
> -#define MLX5_ETH_WQE_FT_META_MACSEC_SHIFT MLX5_ETH_WQE_FT_META_SHIFT
> +#define MLX5_ETH_WQE_FT_META_MACSEC_MASK GENMASK(7, 0)
>   
>   /* MACsec fs_id handling for steering */
>   #define mlx5_macsec_fs_set_tx_fs_id(fs_id) \
> -	(((MLX5_ETH_WQE_FT_META_MACSEC) >> MLX5_ETH_WQE_FT_META_MACSEC_SHIFT) \
> -	 | ((fs_id) << 2))
> +	(MLX5_ETH_WQE_FT_META_IPSEC | (fs_id) << 2)
>   
>   #define MLX5_MACSEC_TX_METADATA(fs_id) \
> -	(mlx5_macsec_fs_set_tx_fs_id(fs_id) << \
> -	 MLX5_ETH_WQE_FT_META_MACSEC_SHIFT)
> +	FIELD_PREP(MLX5_ETH_WQE_FT_META_MACSEC_MASK, \
> +		   mlx5_macsec_fs_set_tx_fs_id(fs_id))
>   
>   /* MACsec fs_id uses 4 bits, supports up to 16 interfaces */
>   #define MLX5_MACSEC_NUM_OF_SUPPORTED_INTERFACES 16
> diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h
> index b21be7630575..5546c7bd2c83 100644
> --- a/include/linux/mlx5/qp.h
> +++ b/include/linux/mlx5/qp.h
> @@ -251,14 +251,9 @@ enum {
>   	MLX5_ETH_WQE_SWP_OUTER_L4_UDP   = 1 << 5,
>   };
>   
> -/* Base shift for metadata bits used by timestamping, IPsec, and MACsec */
> -#define MLX5_ETH_WQE_FT_META_SHIFT 0
> -
>   enum {
> -	MLX5_ETH_WQE_FT_META_IPSEC = BIT(0) << MLX5_ETH_WQE_FT_META_SHIFT,
> -	MLX5_ETH_WQE_FT_META_MACSEC = BIT(1) << MLX5_ETH_WQE_FT_META_SHIFT,
> -	MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK =
> -		GENMASK(5, 2) << MLX5_ETH_WQE_FT_META_SHIFT,
> +	MLX5_ETH_WQE_FT_META_IPSEC = BIT(0),
> +	MLX5_ETH_WQE_FT_META_MACSEC = BIT(1),
>   };
>   
>   struct mlx5_wqe_eth_seg {


Hi Simon,

Thanks for the suggestion!

The goal with this patch was to clearly show which bits are used for
each feature in the metadata field, rather than compressing everything
under a single mask. That’s why we chose to explicitly define MACsec,
FS_ID_MASK, and the shift separately. This way, its easy to see at a
glance that MACsec uses bit 1, and bits 2–5 are reserved for the fs_id.

Using FIELD_PREP can work, but it hides the bit layout behind one
mask, which makes it harder to reason about when multiple features
share the same 32-bit field. We wanted to keep things more readable
and maintainable by showing the bit assignments explicitly.

Carolina

Re: [PATCH mlx5-next 2/3] net/mlx5: Refactor MACsec WQE metadata shifts

[Simon Horman]

On Mon, Sep 15, 2025 at 09:23:04AM +0300, Carolina Jubran wrote:
> 
> On 12/09/2025 18:49, Simon Horman wrote:
> > On Thu, Sep 11, 2025 at 10:10:18AM +0300, Tariq Toukan wrote:
> > > From: Carolina Jubran <cjubran@nvidia.com>

...

> Hi Simon,
> 
> Thanks for the suggestion!
> 
> The goal with this patch was to clearly show which bits are used for
> each feature in the metadata field, rather than compressing everything
> under a single mask. That’s why we chose to explicitly define MACsec,
> FS_ID_MASK, and the shift separately. This way, its easy to see at a
> glance that MACsec uses bit 1, and bits 2–5 are reserved for the fs_id.
> 
> Using FIELD_PREP can work, but it hides the bit layout behind one
> mask, which makes it harder to reason about when multiple features
> share the same 32-bit field. We wanted to keep things more readable
> and maintainable by showing the bit assignments explicitly.
> 
> Carolina

Hi Carolina.

Thanks for your response.
If this is a deliberate choice then I'm happy with the current approach.

Reviewed-by: Simon Horman <horms@kernel.org>

[PATCH mlx5-next 3/3] net/mlx5e: Prevent WQE metadata conflicts between timestamping and offloads

[Tariq Toukan]

From: Carolina Jubran <cjubran@nvidia.com>

Update the WQE metadata assignment to avoid overriding existing
metadata when setting the sysport timestamp ID. Since timestamp IDs are
limited to 256 values, they use only the lower 8 bits of the metadata
field.

To avoid conflicts, move IPsec and MACsec metadata ID to bits 8 and 9,
and shift the MACsec fs_id accordingly. This ensures safe coexistence
of timestamping and offload features that use the same metadata field.

Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Jianbo Liu <jianbol@nvidia.com>
Reviewed-by: Patrisious Haddad <phaddad@nvidia.com>
Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/en_tx.c         | 2 +-
 drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c | 2 +-
 include/linux/mlx5/qp.h                                 | 5 +++--
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c
index 319061d31602..6c55b67b7335 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c
@@ -653,7 +653,7 @@ static void mlx5e_cqe_ts_id_eseg(struct mlx5e_ptpsq *ptpsq, struct sk_buff *skb,
 				 struct mlx5_wqe_eth_seg *eseg)
 {
 	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
-		eseg->flow_table_metadata =
+		eseg->flow_table_metadata |=
 			cpu_to_be32(mlx5e_ptp_metadata_fifo_peek(&ptpsq->metadata_freelist));
 }
 
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c
index 9ec450603176..e6be2f01daf4 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c
@@ -2219,7 +2219,7 @@ static int mlx5_macsec_fs_add_roce_rule_tx(struct mlx5_macsec_fs *macsec_fs, u32
 		 mlx5_macsec_fs_set_tx_fs_id(fs_id));
 	MLX5_SET(set_action_in, action, offset,
 		 MLX5_ETH_WQE_FT_META_MACSEC_SHIFT);
-	MLX5_SET(set_action_in, action, length, 32);
+	MLX5_SET(set_action_in, action, length, 8);
 
 	modify_hdr = mlx5_modify_header_alloc(mdev, MLX5_FLOW_NAMESPACE_RDMA_TX_MACSEC,
 					      1, action);
diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h
index b21be7630575..d67aedc6ea68 100644
--- a/include/linux/mlx5/qp.h
+++ b/include/linux/mlx5/qp.h
@@ -251,8 +251,9 @@ enum {
 	MLX5_ETH_WQE_SWP_OUTER_L4_UDP   = 1 << 5,
 };
 
-/* Base shift for metadata bits used by timestamping, IPsec, and MACsec */
-#define MLX5_ETH_WQE_FT_META_SHIFT 0
+/* Metadata bits 0-7 are used by timestamping */
+/* Base shift for metadata bits used by IPsec and MACsec */
+#define MLX5_ETH_WQE_FT_META_SHIFT 8
 
 enum {
 	MLX5_ETH_WQE_FT_META_IPSEC = BIT(0) << MLX5_ETH_WQE_FT_META_SHIFT,
-- 
2.31.1

Re: [PATCH mlx5-next 3/3] net/mlx5e: Prevent WQE metadata conflicts between timestamping and offloads

[Simon Horman]

On Thu, Sep 11, 2025 at 10:10:19AM +0300, Tariq Toukan wrote:
> From: Carolina Jubran <cjubran@nvidia.com>
> 
> Update the WQE metadata assignment to avoid overriding existing
> metadata when setting the sysport timestamp ID. Since timestamp IDs are
> limited to 256 values, they use only the lower 8 bits of the metadata
> field.
> 
> To avoid conflicts, move IPsec and MACsec metadata ID to bits 8 and 9,
> and shift the MACsec fs_id accordingly. This ensures safe coexistence
> of timestamping and offload features that use the same metadata field.
> 
> Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
> Reviewed-by: Jianbo Liu <jianbol@nvidia.com>
> Reviewed-by: Patrisious Haddad <phaddad@nvidia.com>
> Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
> Signed-off-by: Tariq Toukan <tariqt@nvidia.com>

Reviewed-by: Simon Horman <horms@kernel.org>

Re: [PATCH mlx5-next 0/3] mlx5-next updates 2025-09-11

[Leon Romanovsky]

On Thu, Sep 11, 2025 at 10:10:16AM +0300, Tariq Toukan wrote:
> Hi,
> 
> This series by Carolina contains cleanups significantly touching shared
> mlx5 net and rdma headers.
> 
> Regards,
> Tariq
> 
> Carolina Jubran (3):
>   net/mlx5: Remove VLAN insertion fields from WQE Ether segment
>   net/mlx5: Refactor MACsec WQE metadata shifts
>   net/mlx5e: Prevent WQE metadata conflicts between timestamping and
>     offloads

Thanks, applied to mlx5-next.