From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: <alejandro.lucero-palau@amd.com>
Cc: <linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
<dan.j.williams@intel.com>, <edward.cree@amd.com>,
<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
<edumazet@google.com>, <dave.jiang@intel.com>,
Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v18 11/20] cxl: Define a driver interface for DPA allocation
Date: Thu, 18 Sep 2025 15:52:22 +0100 [thread overview]
Message-ID: <20250918155222.00003bdb@huawei.com> (raw)
In-Reply-To: <20250918091746.2034285-12-alejandro.lucero-palau@amd.com>
On Thu, 18 Sep 2025 10:17:37 +0100
alejandro.lucero-palau@amd.com wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> Region creation involves finding available DPA (device-physical-address)
> capacity to map into HPA (host-physical-address) space.
>
> In order to support CXL Type2 devices, define an API, cxl_request_dpa(),
> that tries to allocate the DPA memory the driver requires to operate.The
> memory requested should not be bigger than the max available HPA obtained
> previously with cxl_get_hpa_freespace().
>
> Based on https://lore.kernel.org/linux-cxl/168592158743.1948938.7622563891193802610.stgit@dwillia2-xfh.jf.intel.com/
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> +
> +/**
> + * cxl_request_dpa - search and reserve DPA given input constraints
> + * @cxlmd: memdev with an endpoint port with available decoders
> + * @mode: DPA operation mode (ram vs pmem)
> + * @alloc: dpa size required
> + *
> + * Returns a pointer to a cxl_endpoint_decoder struct or an error
> + *
> + * Given that a region needs to allocate from limited HPA capacity it
> + * may be the case that a device has more mappable DPA capacity than
> + * available HPA. The expectation is that @alloc is a driver known
> + * value based on the device capacity but it could not be available
> + * due to HPA constraints.
> + *
> + * Returns a pinned cxl_decoder with at least @alloc bytes of capacity
> + * reserved, or an error pointer. The caller is also expected to own the
> + * lifetime of the memdev registration associated with the endpoint to
> + * pin the decoder registered as well.
> + */
> +struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_memdev *cxlmd,
> + enum cxl_partition_mode mode,
> + resource_size_t alloc)
> +{
> + struct cxl_endpoint_decoder *cxled __free(put_cxled) =
> + cxl_find_free_decoder(cxlmd);
I've no idea where this style comes from. Local style in this file seems to be
the more common (I think?)
struct cxl_endpoint_decoder *cxled __free(put_cxled) =
cxl_find_free_decoder(cxlmd);
> + int rc;
> +
> + if (!IS_ALIGNED(alloc, SZ_256M))
> + return ERR_PTR(-EINVAL);
> +
> + if (!cxled)
> + return ERR_PTR(-ENODEV);
> +
> + rc = cxl_dpa_set_part(cxled, mode);
> + if (rc)
> + return ERR_PTR(rc);
> +
> + rc = cxl_dpa_alloc(cxled, alloc);
> + if (rc)
> + return ERR_PTR(rc);
> +
> + return no_free_ptr(cxled);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_request_dpa, "CXL");
next prev parent reply other threads:[~2025-09-18 14:52 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-18 9:17 [PATCH v18 00/20] Type2 device basic support alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 01/20] cxl: Add type2 " alejandro.lucero-palau
2025-09-18 10:55 ` Jonathan Cameron
2025-09-23 11:21 ` Alejandro Lucero Palau
2025-09-29 10:21 ` Alejandro Lucero Palau
2025-09-30 14:43 ` Jonathan Cameron
2025-09-22 21:08 ` Cheatham, Benjamin
2025-09-23 11:43 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 02/20] sfc: add cxl support alejandro.lucero-palau
2025-09-18 23:25 ` Dave Jiang
2025-09-18 9:17 ` [PATCH v18 03/20] cxl: Move pci generic code alejandro.lucero-palau
2025-09-22 21:10 ` Cheatham, Benjamin
2025-09-25 9:27 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 04/20] cxl: allow Type2 drivers to map cxl component regs alejandro.lucero-palau
2025-09-18 11:03 ` Jonathan Cameron
2025-09-24 8:25 ` Alejandro Lucero Palau
2025-09-25 8:53 ` Alejandro Lucero Palau
2025-09-18 23:30 ` Dave Jiang
2025-09-22 21:08 ` Cheatham, Benjamin
2025-09-24 8:36 ` Alejandro Lucero Palau
2025-10-01 23:20 ` PJ Waskiewicz
2025-10-02 9:36 ` Alejandro Lucero Palau
2025-10-07 21:23 ` PJ Waskiewicz
2025-09-18 9:17 ` [PATCH v18 05/20] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-09-18 23:38 ` Dave Jiang
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-18 9:17 ` [PATCH v18 06/20] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-09-22 21:10 ` Cheatham, Benjamin
2025-09-24 8:44 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 07/20] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-09-18 11:08 ` Jonathan Cameron
2025-09-19 15:59 ` Dave Jiang
2025-09-19 19:58 ` Dave Jiang
2025-09-24 8:56 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 08/20] cx/memdev: Indicate probe deferral alejandro.lucero-palau
2025-09-18 11:19 ` Jonathan Cameron
2025-09-19 17:53 ` Dave Jiang
2025-09-24 16:11 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 09/20] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-09-18 14:35 ` Jonathan Cameron
2025-09-24 16:16 ` Alejandro Lucero Palau
2025-09-30 14:47 ` Jonathan Cameron
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-24 16:53 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 10/20] sfc: get root decoder alejandro.lucero-palau
2025-09-19 18:20 ` Dave Jiang
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-18 9:17 ` [PATCH v18 11/20] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-09-18 14:52 ` Jonathan Cameron [this message]
2025-09-25 9:18 ` Alejandro Lucero Palau
2025-09-19 19:46 ` Dave Jiang
2025-09-25 9:21 ` Alejandro Lucero Palau
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-25 9:25 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 12/20] sfc: get endpoint decoder alejandro.lucero-palau
2025-09-18 14:53 ` Jonathan Cameron
2025-09-25 9:45 ` Alejandro Lucero Palau
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-25 9:48 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 13/20] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 14/20] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 15/20] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 16/20] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-09-18 14:58 ` Jonathan Cameron
2025-09-19 20:59 ` Dave Jiang
2025-09-26 8:59 ` Alejandro Lucero Palau
2025-09-30 0:52 ` Dave Jiang
2025-10-06 7:12 ` Alejandro Lucero Palau
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-26 9:01 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 17/20] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2025-09-19 21:16 ` Dave Jiang
2025-09-22 21:09 ` Cheatham, Benjamin
2025-09-18 9:17 ` [PATCH v18 18/20] sfc: create cxl region alejandro.lucero-palau
2025-09-18 15:03 ` Jonathan Cameron
2025-09-26 9:27 ` Alejandro Lucero Palau
2025-09-18 9:17 ` [PATCH v18 19/20] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-09-18 9:17 ` [PATCH v18 20/20] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-09-18 15:08 ` Jonathan Cameron
2025-09-26 9:47 ` Alejandro Lucero Palau
2025-09-30 14:51 ` Jonathan Cameron
2025-09-19 12:51 ` [PATCH v18 00/20] Type2 device basic support Alejandro Lucero Palau
2025-09-19 16:26 ` Dave Jiang
2025-09-19 16:55 ` Alejandro Lucero Palau
2025-09-19 21:42 ` Dave Jiang
2025-09-23 10:35 ` Alejandro Lucero Palau
2025-09-23 18:28 ` Dave Jiang
2025-09-22 21:10 ` Cheatham, Benjamin
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