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From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Alejandro Lucero Palau <alucerop@amd.com>
Cc: <alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
	<netdev@vger.kernel.org>, <dan.j.williams@intel.com>,
	<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
	<pabeni@redhat.com>, <edumazet@google.com>,
	<dave.jiang@intel.com>
Subject: Re: [PATCH v18 09/20] cxl: Define a driver interface for HPA free space enumeration
Date: Tue, 30 Sep 2025 15:47:19 +0100	[thread overview]
Message-ID: <20250930154719.000000fd@huawei.com> (raw)
In-Reply-To: <989dd1bf-adcd-4bd4-82fc-0497d615667a@amd.com>

On Wed, 24 Sep 2025 17:16:14 +0100
Alejandro Lucero Palau <alucerop@amd.com> wrote:

> On 9/18/25 15:35, Jonathan Cameron wrote:
> > On Thu, 18 Sep 2025 10:17:35 +0100
> > <alejandro.lucero-palau@amd.com> wrote:
> >  
> >> From: Alejandro Lucero <alucerop@amd.com>
> >>
> >> CXL region creation involves allocating capacity from Device Physical Address
> >> (DPA) and assigning it to decode a given Host Physical Address (HPA). Before
> >> determining how much DPA to allocate the amount of available HPA must be
> >> determined. Also, not all HPA is created equal, some HPA targets RAM, some
> >> targets PMEM, some is prepared for device-memory flows like HDM-D and HDM-DB,
> >> and some is HDM-H (host-only).
> >>
> >> In order to support Type2 CXL devices, wrap all of those concerns into
> >> an API that retrieves a root decoder (platform CXL window) that fits the
> >> specified constraints and the capacity available for a new region.
> >>
> >> Add a complementary function for releasing the reference to such root
> >> decoder.
> >>
> >> Based on https://lore.kernel.org/linux-cxl/168592159290.1948938.13522227102445462976.stgit@dwillia2-xfh.jf.intel.com/
> >>
> >> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> >> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>  
> > Either I was half asleep or a few things have snuck in.
> >
> > See below.
> >  
> >> +
> >> +/**
> >> + * cxl_get_hpa_freespace - find a root decoder with free capacity per constraints
> >> + * @endpoint: the endpoint requiring the HPA  
> > The parameter seems to have changed.  Make sure to point scripts/kernel-doc at each
> > file to check for stuff like this.  
> 
> 
> OK.
> 
> 
> >  
> >> + * @interleave_ways: number of entries in @host_bridges
> >> + * @flags: CXL_DECODER_F flags for selecting RAM vs PMEM, and Type2 device
> >> + * @max_avail_contig: output parameter of max contiguous bytes available in the
> >> + *		      returned decoder
> >> + *
> >> + * Returns a pointer to a struct cxl_root_decoder
> >> + *
> >> + * The return tuple of a 'struct cxl_root_decoder' and 'bytes available given
> >> + * in (@max_avail_contig))' is a point in time snapshot. If by the time the
> >> + * caller goes to use this root decoder's capacity the capacity is reduced then
> >> + * caller needs to loop and retry.
> >> + *
> >> + * The returned root decoder has an elevated reference count that needs to be
> >> + * put with cxl_put_root_decoder(cxlrd).
> >> + */
> >> +struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_memdev *cxlmd,
> >> +					       int interleave_ways,
> >> +					       unsigned long flags,
> >> +					       resource_size_t *max_avail_contig)
> >> +{
> >> +	struct cxl_root *root __free(put_cxl_root) = NULL;  
> > Nope to this.  See the stuff in cleanup.h on why not.  
> 
> 
> I guess you mean to declare the pointer later on when assigned to the 
> object instead of a default NULL, as you point out later.

yes.

> 
> After reading the cleanup file, it is not clear to me if this is really 
> needed since there is no lock involved in that example for a potential bug.
> 

Do it anyway. It's not about bugs today, but about fragile code patterns that
may break later without it being obvious.

> 
> >> +	struct cxl_port *endpoint = cxlmd->endpoint;
> >> +	struct cxlrd_max_context ctx = {
> >> +		.host_bridges = &endpoint->host_bridge,
> >> +		.flags = flags,
> >> +	};
> >> +	struct cxl_port *root_port;
> >> +
> >> +	if (!endpoint) {
> >> +		dev_dbg(&cxlmd->dev, "endpoint not linked to memdev\n");
> >> +		return ERR_PTR(-ENXIO);
> >> +	}
> >> +
> >> +	root  = find_cxl_root(endpoint);  
> > extra space, but should be
> > 	struct cxl_root *root __free(put_cxl_root) = find_cxl_root(endpoint);
> > anyway.
> >  



  reply	other threads:[~2025-09-30 14:47 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-18  9:17 [PATCH v18 00/20] Type2 device basic support alejandro.lucero-palau
2025-09-18  9:17 ` [PATCH v18 01/20] cxl: Add type2 " alejandro.lucero-palau
2025-09-18 10:55   ` Jonathan Cameron
2025-09-23 11:21     ` Alejandro Lucero Palau
2025-09-29 10:21       ` Alejandro Lucero Palau
2025-09-30 14:43         ` Jonathan Cameron
2025-09-22 21:08   ` Cheatham, Benjamin
2025-09-23 11:43     ` Alejandro Lucero Palau
2025-09-18  9:17 ` [PATCH v18 02/20] sfc: add cxl support alejandro.lucero-palau
2025-09-18 23:25   ` Dave Jiang
2025-09-18  9:17 ` [PATCH v18 03/20] cxl: Move pci generic code alejandro.lucero-palau
2025-09-22 21:10   ` Cheatham, Benjamin
2025-09-25  9:27     ` Alejandro Lucero Palau
2025-09-18  9:17 ` [PATCH v18 04/20] cxl: allow Type2 drivers to map cxl component regs alejandro.lucero-palau
2025-09-18 11:03   ` Jonathan Cameron
2025-09-24  8:25     ` Alejandro Lucero Palau
2025-09-25  8:53       ` Alejandro Lucero Palau
2025-09-18 23:30   ` Dave Jiang
2025-09-22 21:08   ` Cheatham, Benjamin
2025-09-24  8:36     ` Alejandro Lucero Palau
2025-10-01 23:20   ` PJ Waskiewicz
2025-10-02  9:36     ` Alejandro Lucero Palau
2025-10-07 21:23       ` PJ Waskiewicz
2025-09-18  9:17 ` [PATCH v18 05/20] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-09-18 23:38   ` Dave Jiang
2025-09-22 21:09   ` Cheatham, Benjamin
2025-09-18  9:17 ` [PATCH v18 06/20] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-09-22 21:10   ` Cheatham, Benjamin
2025-09-24  8:44     ` Alejandro Lucero Palau
2025-09-18  9:17 ` [PATCH v18 07/20] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-09-18 11:08   ` Jonathan Cameron
2025-09-19 15:59   ` Dave Jiang
2025-09-19 19:58     ` Dave Jiang
2025-09-24  8:56       ` Alejandro Lucero Palau
2025-09-18  9:17 ` [PATCH v18 08/20] cx/memdev: Indicate probe deferral alejandro.lucero-palau
2025-09-18 11:19   ` Jonathan Cameron
2025-09-19 17:53   ` Dave Jiang
2025-09-24 16:11     ` Alejandro Lucero Palau
2025-09-18  9:17 ` [PATCH v18 09/20] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-09-18 14:35   ` Jonathan Cameron
2025-09-24 16:16     ` Alejandro Lucero Palau
2025-09-30 14:47       ` Jonathan Cameron [this message]
2025-09-22 21:09   ` Cheatham, Benjamin
2025-09-24 16:53     ` Alejandro Lucero Palau
2025-09-18  9:17 ` [PATCH v18 10/20] sfc: get root decoder alejandro.lucero-palau
2025-09-19 18:20   ` Dave Jiang
2025-09-22 21:09   ` Cheatham, Benjamin
2025-09-18  9:17 ` [PATCH v18 11/20] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-09-18 14:52   ` Jonathan Cameron
2025-09-25  9:18     ` Alejandro Lucero Palau
2025-09-19 19:46   ` Dave Jiang
2025-09-25  9:21     ` Alejandro Lucero Palau
2025-09-22 21:09   ` Cheatham, Benjamin
2025-09-25  9:25     ` Alejandro Lucero Palau
2025-09-18  9:17 ` [PATCH v18 12/20] sfc: get endpoint decoder alejandro.lucero-palau
2025-09-18 14:53   ` Jonathan Cameron
2025-09-25  9:45     ` Alejandro Lucero Palau
2025-09-22 21:09   ` Cheatham, Benjamin
2025-09-25  9:48     ` Alejandro Lucero Palau
2025-09-18  9:17 ` [PATCH v18 13/20] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-09-18  9:17 ` [PATCH v18 14/20] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-09-18  9:17 ` [PATCH v18 15/20] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-09-18  9:17 ` [PATCH v18 16/20] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-09-18 14:58   ` Jonathan Cameron
2025-09-19 20:59   ` Dave Jiang
2025-09-26  8:59     ` Alejandro Lucero Palau
2025-09-30  0:52       ` Dave Jiang
2025-10-06  7:12         ` Alejandro Lucero Palau
2025-09-22 21:09   ` Cheatham, Benjamin
2025-09-26  9:01     ` Alejandro Lucero Palau
2025-09-18  9:17 ` [PATCH v18 17/20] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2025-09-19 21:16   ` Dave Jiang
2025-09-22 21:09   ` Cheatham, Benjamin
2025-09-18  9:17 ` [PATCH v18 18/20] sfc: create cxl region alejandro.lucero-palau
2025-09-18 15:03   ` Jonathan Cameron
2025-09-26  9:27     ` Alejandro Lucero Palau
2025-09-18  9:17 ` [PATCH v18 19/20] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-09-18  9:17 ` [PATCH v18 20/20] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-09-18 15:08   ` Jonathan Cameron
2025-09-26  9:47     ` Alejandro Lucero Palau
2025-09-30 14:51       ` Jonathan Cameron
2025-09-19 12:51 ` [PATCH v18 00/20] Type2 device basic support Alejandro Lucero Palau
2025-09-19 16:26 ` Dave Jiang
2025-09-19 16:55   ` Alejandro Lucero Palau
2025-09-19 21:42     ` Dave Jiang
2025-09-23 10:35       ` Alejandro Lucero Palau
2025-09-23 18:28         ` Dave Jiang
2025-09-22 21:10 ` Cheatham, Benjamin

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