From: "Niklas Söderlund" <niklas.soderlund@ragnatech.se>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Paul Barker <paul@pbarker.dev>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>,
netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
linux-kernel@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
stable@vger.kernel.org
Subject: Re: [PATCH 3/3] net: ravb: Enforce descriptor type ordering to prevent early DMA start
Date: Wed, 15 Oct 2025 17:56:22 +0200 [thread overview]
Message-ID: <20251015155622.GE439570@ragnatech.se> (raw)
In-Reply-To: <20251015150026.117587-4-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
Thanks for your work.
On 2025-10-15 16:00:26 +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Ensure TX descriptor type fields are written in a safe order so the DMA
> engine does not begin processing a chain before all descriptors are
> fully initialised.
>
> For multi-descriptor transmissions the driver writes DT_FEND into the
> last descriptor and DT_FSTART into the first. The DMA engine starts
> processing when it sees DT_FSTART. If the compiler or CPU reorders the
> writes and publishes DT_FSTART before DT_FEND, the DMA can start early
> and process an incomplete chain, leading to corrupted transmissions or
> DMA errors.
>
> Fix this by writing DT_FEND before the dma_wmb() barrier, executing
> dma_wmb() immediately before DT_FSTART (or DT_FSINGLE in the single
> descriptor case), and then adding a wmb() after the type updates to
> ensure CPU-side ordering before ringing the hardware doorbell.
>
> On an RZ/G2L platform running an RT kernel, this reordering hazard was
> observed as TX stalls and timeouts:
>
> [ 372.968431] NETDEV WATCHDOG: end0 (ravb): transmit queue 0 timed out
> [ 372.968494] WARNING: CPU: 0 PID: 10 at net/sched/sch_generic.c:467 dev_watchdog+0x4a4/0x4ac
> [ 373.969291] ravb 11c20000.ethernet end0: transmit timed out, status 00000000, resetting...
>
> This change enforces the required ordering and prevents the DMA engine
> from observing DT_FSTART before the rest of the descriptor chain is
> valid.
>
> Fixes: 2f45d1902acf ("ravb: minimize TX data copying")
> Cc: stable@vger.kernel.org
> Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> drivers/net/ethernet/renesas/ravb_main.c | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
> index a200e205825a..2a995fa9bfff 100644
> --- a/drivers/net/ethernet/renesas/ravb_main.c
> +++ b/drivers/net/ethernet/renesas/ravb_main.c
> @@ -2211,15 +2211,19 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
>
> skb_tx_timestamp(skb);
> }
> - /* Descriptor type must be set after all the above writes */
> - dma_wmb();
> +
> + /* For multi-descriptors set DT_FEND before calling dma_wmb() */
> if (num_tx_desc > 1) {
> desc->die_dt = DT_FEND;
> desc--;
> - desc->die_dt = DT_FSTART;
> - } else {
> - desc->die_dt = DT_FSINGLE;
> }
> +
> + /* Descriptor type must be set after all the above writes */
> + dma_wmb();
> + desc->die_dt = (num_tx_desc > 1) ? DT_FSTART : DT_FSINGLE;
IMHO it's ugly to evaluate num_tx_desc twice. I would rather just open
code the full steps in each branch of the if above. It would make it
easier to read and understand.
> +
> + /* Ensure data is written to RAM before initiating DMA transfer */
> + wmb();
All of this looks a bit odd, why not just do a single dma_wmb() or wmb()
before ringing the doorbell? Maybe I'm missing something obvious?
> ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
>
> priv->cur_tx[q] += num_tx_desc;
> --
> 2.43.0
>
--
Kind Regards,
Niklas Söderlund
next prev parent reply other threads:[~2025-10-15 15:56 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 15:00 [PATCH 0/3] net: ravb: Fix SoC-specific configuration and descriptor handling issues Prabhakar
2025-10-15 15:00 ` [PATCH 1/3] net: ravb: Make DBAT entry count configurable per-SoC Prabhakar
2025-10-15 15:35 ` Niklas Söderlund
2025-10-15 17:05 ` Lad, Prabhakar
2025-10-15 17:29 ` Niklas Söderlund
2025-10-15 15:00 ` [PATCH 2/3] net: ravb: Allocate correct number of queues based on SoC support Prabhakar
2025-10-15 15:45 ` Niklas Söderlund
2025-10-15 15:00 ` [PATCH 3/3] net: ravb: Enforce descriptor type ordering to prevent early DMA start Prabhakar
2025-10-15 15:56 ` Niklas Söderlund [this message]
2025-10-15 17:01 ` Lad, Prabhakar
2025-10-15 17:28 ` Niklas Söderlund
2025-10-16 12:00 ` Fabrizio Castro
2025-10-16 12:39 ` niklas.soderlund
2025-10-17 10:22 ` Fabrizio Castro
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