* [PATCH net-next v2 1/4] net: stmmac: socfpga: Agilex5 EMAC platform configuration
2025-10-31 17:27 [PATCH net-next v2 0/4] net: stmmac: socfpga: Add Agilex5 platform support and enhancements Rohan G Thomas via B4 Relay
@ 2025-10-31 17:27 ` Rohan G Thomas via B4 Relay
2025-10-31 17:27 ` [PATCH net-next v2 2/4] net: stmmac: socfpga: Enable TBS support for Agilex5 Rohan G Thomas via B4 Relay
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Rohan G Thomas via B4 Relay @ 2025-10-31 17:27 UTC (permalink / raw)
To: Maxime Chevallier, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Alexandre Torgue,
Richard Cochran, Steffen Trumtrar
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel,
Rohan G Thomas
From: Rohan G Thomas <rohan.g.thomas@altera.com>
Agilex5 HPS EMAC uses the dwxgmac-3.10a IP, unlike previous socfpga
platforms which use dwmac1000 IP. Due to differences in platform
configuration, Agilex5 requires a distinct setup.
Introduce a setup_plat_dat() callback in socfpga_dwmac_ops to handle
platform-specific setup. This callback is invoked before
stmmac_dvr_probe() to ensure the platform data is correctly
configured. Also, implemented separate setup_plat_dat() callback for
current socfpga platforms and Agilex5.
Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 30 +++++++++++++++++++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 2ff5db6d41ca08a1652d57f3eb73923b9a9558bf..5666b01723643984f21b996e7653a36f4dc22e30 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -44,6 +44,7 @@
struct socfpga_dwmac;
struct socfpga_dwmac_ops {
int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv);
+ void (*setup_plat_dat)(struct socfpga_dwmac *dwmac_priv);
};
struct socfpga_dwmac {
@@ -441,6 +442,23 @@ static int socfpga_dwmac_init(struct platform_device *pdev, void *bsp_priv)
return dwmac->ops->set_phy_mode(dwmac);
}
+static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac)
+{
+ struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
+
+ plat_dat->core_type = DWMAC_CORE_GMAC;
+
+ /* Rx watchdog timer in dwmac is buggy in this hw */
+ plat_dat->riwt_off = 1;
+}
+
+static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)
+{
+ struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
+
+ plat_dat->core_type = DWMAC_CORE_XGMAC;
+}
+
static int socfpga_dwmac_probe(struct platform_device *pdev)
{
struct plat_stmmacenet_data *plat_dat;
@@ -497,25 +515,31 @@ static int socfpga_dwmac_probe(struct platform_device *pdev)
plat_dat->pcs_init = socfpga_dwmac_pcs_init;
plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
plat_dat->select_pcs = socfpga_dwmac_select_pcs;
- plat_dat->core_type = DWMAC_CORE_GMAC;
- plat_dat->riwt_off = 1;
+ ops->setup_plat_dat(dwmac);
return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
}
static const struct socfpga_dwmac_ops socfpga_gen5_ops = {
.set_phy_mode = socfpga_gen5_set_phy_mode,
+ .setup_plat_dat = socfpga_gen5_setup_plat_dat,
};
static const struct socfpga_dwmac_ops socfpga_gen10_ops = {
.set_phy_mode = socfpga_gen10_set_phy_mode,
+ .setup_plat_dat = socfpga_gen5_setup_plat_dat,
+};
+
+static const struct socfpga_dwmac_ops socfpga_agilex5_ops = {
+ .set_phy_mode = socfpga_gen10_set_phy_mode,
+ .setup_plat_dat = socfpga_agilex5_setup_plat_dat,
};
static const struct of_device_id socfpga_dwmac_match[] = {
{ .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops },
{ .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops },
- { .compatible = "altr,socfpga-stmmac-agilex5", .data = &socfpga_gen10_ops },
+ { .compatible = "altr,socfpga-stmmac-agilex5", .data = &socfpga_agilex5_ops },
{ }
};
MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
--
2.43.7
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH net-next v2 2/4] net: stmmac: socfpga: Enable TBS support for Agilex5
2025-10-31 17:27 [PATCH net-next v2 0/4] net: stmmac: socfpga: Add Agilex5 platform support and enhancements Rohan G Thomas via B4 Relay
2025-10-31 17:27 ` [PATCH net-next v2 1/4] net: stmmac: socfpga: Agilex5 EMAC platform configuration Rohan G Thomas via B4 Relay
@ 2025-10-31 17:27 ` Rohan G Thomas via B4 Relay
2025-10-31 17:27 ` [PATCH net-next v2 3/4] net: stmmac: socfpga: Enable TSO for Agilex5 platform Rohan G Thomas via B4 Relay
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Rohan G Thomas via B4 Relay @ 2025-10-31 17:27 UTC (permalink / raw)
To: Maxime Chevallier, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Alexandre Torgue,
Richard Cochran, Steffen Trumtrar
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel,
Rohan G Thomas
From: Rohan G Thomas <rohan.g.thomas@altera.com>
Agilex5 supports Time-Based Scheduling(TBS) for Tx queue 6 and Tx
queue 7. This commit enables TBS support for these queues.
Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 5666b01723643984f21b996e7653a36f4dc22e30..4f256f0ae05c15d28e4836d676e2f2c052540184 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -457,6 +457,19 @@ static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)
struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
plat_dat->core_type = DWMAC_CORE_XGMAC;
+
+ /* Enable TBS */
+ switch (plat_dat->tx_queues_to_use) {
+ case 8:
+ plat_dat->tx_queues_cfg[7].tbs_en = true;
+ fallthrough;
+ case 7:
+ plat_dat->tx_queues_cfg[6].tbs_en = true;
+ break;
+ default:
+ /* Tx Queues 0 - 5 doesn't support TBS on Agilex5 */
+ break;
+ }
}
static int socfpga_dwmac_probe(struct platform_device *pdev)
--
2.43.7
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH net-next v2 3/4] net: stmmac: socfpga: Enable TSO for Agilex5 platform
2025-10-31 17:27 [PATCH net-next v2 0/4] net: stmmac: socfpga: Add Agilex5 platform support and enhancements Rohan G Thomas via B4 Relay
2025-10-31 17:27 ` [PATCH net-next v2 1/4] net: stmmac: socfpga: Agilex5 EMAC platform configuration Rohan G Thomas via B4 Relay
2025-10-31 17:27 ` [PATCH net-next v2 2/4] net: stmmac: socfpga: Enable TBS support for Agilex5 Rohan G Thomas via B4 Relay
@ 2025-10-31 17:27 ` Rohan G Thomas via B4 Relay
2025-10-31 17:27 ` [PATCH net-next v2 4/4] net: stmmac: socfpga: Add hardware supported cross-timestamp Rohan G Thomas via B4 Relay
2025-11-06 2:40 ` [PATCH net-next v2 0/4] net: stmmac: socfpga: Add Agilex5 platform support and enhancements patchwork-bot+netdevbpf
4 siblings, 0 replies; 6+ messages in thread
From: Rohan G Thomas via B4 Relay @ 2025-10-31 17:27 UTC (permalink / raw)
To: Maxime Chevallier, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Alexandre Torgue,
Richard Cochran, Steffen Trumtrar
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel,
Rohan G Thomas
From: Rohan G Thomas <rohan.g.thomas@altera.com>
Agilex5 supports TCP Segmentation Offload(TSO). This commit enables
TSO for Agilex5 socfpga platforms.
Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 4f256f0ae05c15d28e4836d676e2f2c052540184..1837346ca2d438018ae161a233f415fe0181c78d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -458,6 +458,9 @@ static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)
plat_dat->core_type = DWMAC_CORE_XGMAC;
+ /* Enable TSO */
+ plat_dat->flags |= STMMAC_FLAG_TSO_EN;
+
/* Enable TBS */
switch (plat_dat->tx_queues_to_use) {
case 8:
--
2.43.7
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH net-next v2 4/4] net: stmmac: socfpga: Add hardware supported cross-timestamp
2025-10-31 17:27 [PATCH net-next v2 0/4] net: stmmac: socfpga: Add Agilex5 platform support and enhancements Rohan G Thomas via B4 Relay
` (2 preceding siblings ...)
2025-10-31 17:27 ` [PATCH net-next v2 3/4] net: stmmac: socfpga: Enable TSO for Agilex5 platform Rohan G Thomas via B4 Relay
@ 2025-10-31 17:27 ` Rohan G Thomas via B4 Relay
2025-11-06 2:40 ` [PATCH net-next v2 0/4] net: stmmac: socfpga: Add Agilex5 platform support and enhancements patchwork-bot+netdevbpf
4 siblings, 0 replies; 6+ messages in thread
From: Rohan G Thomas via B4 Relay @ 2025-10-31 17:27 UTC (permalink / raw)
To: Maxime Chevallier, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Alexandre Torgue,
Richard Cochran, Steffen Trumtrar
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel,
Rohan G Thomas
From: Rohan G Thomas <rohan.g.thomas@altera.com>
Cross timestamping is supported on Agilex5 platform with Synchronized
Multidrop Timestamp Gathering(SMTG) IP. The hardware cross-timestamp
result is made available the applications through the ioctl call
PTP_SYS_OFFSET_PRECISE, which inturn calls stmmac_getcrosststamp().
Device time is stored in the MAC Auxiliary register. The 64-bit System
time (ARM_ARCH_COUNTER) is stored in SMTG IP. SMTG IP is an MDIO device
with 0xC - 0xF MDIO register space holds 64-bit system time.
This commit is similar to following commit for Intel platforms:
Commit 341f67e424e5 ("net: stmmac: Add hardware supported cross-timestamp")
Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 120 +++++++++++++++++++++
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 5 +
2 files changed, 125 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 1837346ca2d438018ae161a233f415fe0181c78d..49d651948e2bd41faeecaebb37121aef757a66a7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -5,6 +5,7 @@
*/
#include <linux/mfd/altera-sysmgr.h>
+#include <linux/clocksource_ids.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_net.h>
@@ -15,8 +16,10 @@
#include <linux/reset.h>
#include <linux/stmmac.h>
+#include "dwxgmac2.h"
#include "stmmac.h"
#include "stmmac_platform.h"
+#include "stmmac_ptp.h"
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
@@ -41,6 +44,13 @@
#define SGMII_ADAPTER_ENABLE 0x0000
#define SGMII_ADAPTER_DISABLE 0x0001
+#define SMTG_MDIO_ADDR 0x15
+#define SMTG_TSC_WORD0 0xC
+#define SMTG_TSC_WORD1 0xD
+#define SMTG_TSC_WORD2 0xE
+#define SMTG_TSC_WORD3 0xF
+#define SMTG_TSC_SHIFT 16
+
struct socfpga_dwmac;
struct socfpga_dwmac_ops {
int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv);
@@ -269,6 +279,112 @@ static int socfpga_set_phy_mode_common(int phymode, u32 *val)
return 0;
}
+static void get_smtgtime(struct mii_bus *mii, int smtg_addr, u64 *smtg_time)
+{
+ u64 ns;
+
+ ns = mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD3);
+ ns <<= SMTG_TSC_SHIFT;
+ ns |= mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD2);
+ ns <<= SMTG_TSC_SHIFT;
+ ns |= mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD1);
+ ns <<= SMTG_TSC_SHIFT;
+ ns |= mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD0);
+
+ *smtg_time = ns;
+}
+
+static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system,
+ void *ctx)
+{
+ struct stmmac_priv *priv = (struct stmmac_priv *)ctx;
+ u32 num_snapshot, gpio_value, acr_value;
+ void __iomem *ptpaddr = priv->ptpaddr;
+ void __iomem *ioaddr = priv->hw->pcsr;
+ unsigned long flags;
+ u64 smtg_time = 0;
+ u64 ptp_time = 0;
+ int i, ret;
+ u32 v;
+
+ /* Both internal crosstimestamping and external triggered event
+ * timestamping cannot be run concurrently.
+ */
+ if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN)
+ return -EBUSY;
+
+ mutex_lock(&priv->aux_ts_lock);
+ /* Enable Internal snapshot trigger */
+ acr_value = readl(ptpaddr + PTP_ACR);
+ acr_value &= ~PTP_ACR_MASK;
+ switch (priv->plat->int_snapshot_num) {
+ case AUX_SNAPSHOT0:
+ acr_value |= PTP_ACR_ATSEN0;
+ break;
+ case AUX_SNAPSHOT1:
+ acr_value |= PTP_ACR_ATSEN1;
+ break;
+ case AUX_SNAPSHOT2:
+ acr_value |= PTP_ACR_ATSEN2;
+ break;
+ case AUX_SNAPSHOT3:
+ acr_value |= PTP_ACR_ATSEN3;
+ break;
+ default:
+ mutex_unlock(&priv->aux_ts_lock);
+ return -EINVAL;
+ }
+ writel(acr_value, ptpaddr + PTP_ACR);
+
+ /* Clear FIFO */
+ acr_value = readl(ptpaddr + PTP_ACR);
+ acr_value |= PTP_ACR_ATSFC;
+ writel(acr_value, ptpaddr + PTP_ACR);
+ /* Release the mutex */
+ mutex_unlock(&priv->aux_ts_lock);
+
+ /* Trigger Internal snapshot signal. Create a rising edge by just toggle
+ * the GPO0 to low and back to high.
+ */
+ gpio_value = readl(ioaddr + XGMAC_GPIO_STATUS);
+ gpio_value &= ~XGMAC_GPIO_GPO0;
+ writel(gpio_value, ioaddr + XGMAC_GPIO_STATUS);
+ gpio_value |= XGMAC_GPIO_GPO0;
+ writel(gpio_value, ioaddr + XGMAC_GPIO_STATUS);
+
+ /* Poll for time sync operation done */
+ ret = readl_poll_timeout(priv->ioaddr + XGMAC_INT_STATUS, v,
+ (v & XGMAC_INT_TSIS), 100, 10000);
+ if (ret) {
+ netdev_err(priv->dev, "%s: Wait for time sync operation timeout\n",
+ __func__);
+ return ret;
+ }
+
+ *system = (struct system_counterval_t) {
+ .cycles = 0,
+ .cs_id = CSID_ARM_ARCH_COUNTER,
+ .use_nsecs = false,
+ };
+
+ num_snapshot = (readl(ioaddr + XGMAC_TIMESTAMP_STATUS) &
+ XGMAC_TIMESTAMP_ATSNS_MASK) >>
+ XGMAC_TIMESTAMP_ATSNS_SHIFT;
+
+ /* Repeat until the timestamps are from the FIFO last segment */
+ for (i = 0; i < num_snapshot; i++) {
+ read_lock_irqsave(&priv->ptp_lock, flags);
+ stmmac_get_ptptime(priv, ptpaddr, &ptp_time);
+ *device = ns_to_ktime(ptp_time);
+ read_unlock_irqrestore(&priv->ptp_lock, flags);
+ }
+
+ get_smtgtime(priv->mii, SMTG_MDIO_ADDR, &smtg_time);
+ system->cycles = smtg_time;
+
+ return 0;
+}
+
static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac)
{
struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
@@ -473,6 +589,10 @@ static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)
/* Tx Queues 0 - 5 doesn't support TBS on Agilex5 */
break;
}
+
+ /* Hw supported cross-timestamp */
+ plat_dat->int_snapshot_num = AUX_SNAPSHOT0;
+ plat_dat->crosststamp = smtg_crosststamp;
}
static int socfpga_dwmac_probe(struct platform_device *pdev)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index 0d408ee17f337851502cbcba8e82d2b839b9db02..e48cfa05000c07ed9194de786efa530a61a9dbfa 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -79,6 +79,7 @@
#define XGMAC_PSRQ(x) GENMASK((x) * 8 + 7, (x) * 8)
#define XGMAC_PSRQ_SHIFT(x) ((x) * 8)
#define XGMAC_INT_STATUS 0x000000b0
+#define XGMAC_INT_TSIS BIT(12)
#define XGMAC_LPIIS BIT(5)
#define XGMAC_PMTIS BIT(4)
#define XGMAC_INT_EN 0x000000b4
@@ -173,6 +174,8 @@
#define XGMAC_MDIO_ADDR 0x00000200
#define XGMAC_MDIO_DATA 0x00000204
#define XGMAC_MDIO_C22P 0x00000220
+#define XGMAC_GPIO_STATUS 0x0000027c
+#define XGMAC_GPIO_GPO0 BIT(16)
#define XGMAC_ADDRx_HIGH(x) (0x00000300 + (x) * 0x8)
#define XGMAC_ADDR_MAX 32
#define XGMAC_AE BIT(31)
@@ -220,6 +223,8 @@
#define XGMAC_OB BIT(0)
#define XGMAC_RSS_DATA 0x00000c8c
#define XGMAC_TIMESTAMP_STATUS 0x00000d20
+#define XGMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25)
+#define XGMAC_TIMESTAMP_ATSNS_SHIFT 25
#define XGMAC_TXTSC BIT(15)
#define XGMAC_TXTIMESTAMP_NSEC 0x00000d30
#define XGMAC_TXTSSTSLO GENMASK(30, 0)
--
2.43.7
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH net-next v2 0/4] net: stmmac: socfpga: Add Agilex5 platform support and enhancements
2025-10-31 17:27 [PATCH net-next v2 0/4] net: stmmac: socfpga: Add Agilex5 platform support and enhancements Rohan G Thomas via B4 Relay
` (3 preceding siblings ...)
2025-10-31 17:27 ` [PATCH net-next v2 4/4] net: stmmac: socfpga: Add hardware supported cross-timestamp Rohan G Thomas via B4 Relay
@ 2025-11-06 2:40 ` patchwork-bot+netdevbpf
4 siblings, 0 replies; 6+ messages in thread
From: patchwork-bot+netdevbpf @ 2025-11-06 2:40 UTC (permalink / raw)
To: Rohan G Thomas
Cc: maxime.chevallier, andrew+netdev, davem, edumazet, kuba, pabeni,
mcoquelin.stm32, alexandre.torgue, richardcochran, s.trumtrar,
netdev, linux-stm32, linux-arm-kernel, linux-kernel
Hello:
This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Sat, 01 Nov 2025 01:27:06 +0800 you wrote:
> This patch series adds support for the Agilex5 EMAC platform to the
> dwmac-socfpga driver.
>
> The series includes:
> - Platform configuration for Agilex5 EMAC
> - Enabling Time-Based Scheduling (TBS) for Tx queues 6 and 7
> - Enabling TCP Segmentation Offload(TSO)
> - Adding hardware-supported cross timestamping using the SMTG IP,
> allowing precise synchronization between MAC and system time via
> PTP_SYS_OFFSET_PRECISE.
>
> [...]
Here is the summary with links:
- [net-next,v2,1/4] net: stmmac: socfpga: Agilex5 EMAC platform configuration
https://git.kernel.org/netdev/net-next/c/93d46ea3e984
- [net-next,v2,2/4] net: stmmac: socfpga: Enable TBS support for Agilex5
https://git.kernel.org/netdev/net-next/c/4c00476d4480
- [net-next,v2,3/4] net: stmmac: socfpga: Enable TSO for Agilex5 platform
https://git.kernel.org/netdev/net-next/c/e28988aef70f
- [net-next,v2,4/4] net: stmmac: socfpga: Add hardware supported cross-timestamp
https://git.kernel.org/netdev/net-next/c/fd8c4f645496
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 6+ messages in thread