[PATCH net-next 08/10] net: renesas: rswitch: add bit access macros for forwarding engine

[Michael Dege <michael.dege@renesas.com>]

Add bit access macros for the forwarding engine needed for L3
routing.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Signed-off-by: Michael Dege <michael.dege@renesas.com>
---
 drivers/net/ethernet/renesas/rswitch.h | 113 ++++++++++++++++++++++++++++++++-
 1 file changed, 112 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/renesas/rswitch.h b/drivers/net/ethernet/renesas/rswitch.h
index ef64bd6e5a75..773bde67bebc 100644
--- a/drivers/net/ethernet/renesas/rswitch.h
+++ b/drivers/net/ethernet/renesas/rswitch.h
@@ -839,7 +839,7 @@ enum rswitch_gwca_mode {
 
 #define CABPPFLC_INIT_VALUE	0x00800080
 
-/* MFWD */
+/* MFWD forwarding engine */
 #define FWPC0(i)		(FWPC00 + (i) * 0x10)
 #define FWPC0_LTHTA		BIT(0)
 #define FWPC0_IP4UE		BIT(3)
@@ -857,6 +857,7 @@ enum rswitch_gwca_mode {
 
 #define FWPC1(i)		(FWPC10 + (i) * 0x10)
 #define FWPC1_LTHFW		GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)
+#define FWPC1_LTHFW_MASK	GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)
 #define FWPC1_DDE		BIT(0)
 
 #define FWPC2(i)		(FWPC20 + (i) * 0x10)
@@ -882,6 +883,116 @@ enum rswitch_gwca_mode {
 #define FWMACAGC_MACAGOG	BIT(28)
 #define FWMACAGC_MACDESOG	BIT(29)
 
+#define FWIP4SC_IDPTS		BIT(24)
+#define FWIP4SC_IIDS		BIT(23)
+#define FWIP4SC_IISS		BIT(22)
+#define FWIP4SC_ICDS		BIT(21)
+#define FWIP4SC_ICPS		BIT(20)
+#define FWIP4SC_ICVS		BIT(19)
+#define FWIP4SC_ISDS		BIT(18)
+#define FWIP4SC_ISPS		BIT(17)
+#define FWIP4SC_ISVS		BIT(16)
+#define FWIP4SC_IDPTH		BIT(8)
+#define FWIP4SC_IIDH		BIT(7)
+#define FWIP4SC_IISH		BIT(6)
+#define FWIP4SC_ICDH		BIT(5)
+#define FWIP4SC_ICPH		BIT(4)
+#define FWIP4SC_ICVH		BIT(3)
+#define FWIP4SC_ISDH		BIT(2)
+#define FWIP4SC_ISPH		BIT(1)
+#define FWIP4SC_ISVH		BIT(0)
+
+#define RSWITCH_MAX_NUM_RRULE	265
+
+#define FWLTHHEC_HMUE		GENMASK(26, 16)
+
+#define FWLTHTL0_ED		BIT(16)
+#define FWLTHTL0_SL		BIT(8)
+
+#define FWLTHTL5_MSDUV		BIT(31)
+#define FWLTHTL5_MSDUN		GENMASK(19, 16)
+#define FWLTHTL5_GATEV		BIT(15)
+#define FWLTHTL5_GATEN		GENMASK(2, 0)
+
+#define FWLTHTL6_MTRV		BIT(31)
+#define FWLTHTL6_MTRN		GENMASK(20, 16)
+#define FWLTHTL6_FRERV		BIT(15)
+#define FWLTHTL6_FRERN		GENMASK(6, 0)
+
+#define FWLTHTL7_SLV		GENMASK(16 + RSWITCH_NUM_AGENTS - 1, 16)
+#define FWLTHTL7_RV		BIT(15)
+#define FWLTHTL7_RN		GENMASK(7, 0)
+
+#define FWLTHTL8(i)		(FWLTHTL80 + (i) * 4)
+#define FWLTHTL8_CSD		GENMASK(6, 0)
+
+#define FWLTHTL9_CME		BIT(21)
+#define FWLTHTL9_EME		BIT(20)
+#define FWLTHTL9_IPU		BIT(19)
+#define FWLTHTL9_IPV		GENMASK(18, 16)
+#define FWLTHTL9_DV		GENMASK(RSWITCH_NUM_AGENTS - 1, 0)
+
+#define FWLTHTLR_L		BIT(31)
+#define FWLTHTLR_LCN		GENMASK(25, 16)
+#define FWLTHTLR_LO		BIT(3)
+#define FWLTHTLR_LEF		BIT(2)
+#define FWLTHTLR_LSF		BIT(1)
+#define FWLTHTLR_LF		BIT(0)
+
+#define FWLTHTIM_TR		BIT(1)
+#define FWLTHTIM_TIOG		BIT(0)
+
+#define FWMACTL0_ED		BIT(16)
+#define FWMACTL0_HLD		BIT(10)
+#define FWMACTL0_DE		BIT(9)
+#define FWMACTL0_SL		BIT(8)
+
+#define FWMACTL3_DSLV		GENMASK(16 + RSWITCH_NUM_AGENTS - 1, 16)
+#define FWMACTL3_SSLV		GENMASK(RSWITCH_NUM_HW - 1, 0)
+
+#define FWMACTL4(i)		(FWMACTL40 + (i) * 4)
+
+#define FWMACTL5_CME		BIT(21)
+#define FWMACTL5_EME		BIT(20)
+#define FWMACTL5_IPU		BIT(19)
+#define FWMACTL5_IPV		GENMASK(18, 16)
+#define FWMACTL5_DV		GENMASK(RSWITCH_NUM_AGENTS - 1, 0)
+
+#define FWMACTLR_L		BIT(31)
+#define FWMACTLR_LCN		GENMASK(25, 16)
+#define FWMACTLR_LO		BIT(3)
+#define FWMACTLR_LEF		BIT(2)
+#define FWMACTLR_LSF		BIT(1)
+#define FWMACTLR_LF		BIT(0)
+
+#define FWL23URL0_PV		GENMASK(16 + RSWITCH_NUM_AGENTS - 1, 16)
+#define FWL23URL0_RN		GENMASK(7, 0)
+
+#define FWL23URL1_RTU		GENMASK(26, 25)
+#define FWL23URL1_SDEIU		BIT(24)
+#define FWL23URL1_SPCPU		BIT(23)
+#define FWL23URL1_SVIDU		BIT(22)
+#define FWL23URL1_CDEIU		BIT(21)
+#define FWL23URL1_CPCPU		BIT(20)
+#define FWL23URL1_CVIDU		BIT(19)
+#define FWL23URL1_MSAU		BIT(18)
+#define FWL23URL1_MDAU		BIT(17)
+#define FWL23URL1_TTLU		BIT(16)
+
+#define FWL23URL3_SDEI		BIT(31)
+#define FWL23URL3_SPCP		GENMASK(30, 28)
+#define FWL23URL3_SVID		GENMASK(27, 16)
+#define FWL23URL3_CDEI		BIT(15)
+#define FWL23URL3_CPCP		GENMASK(14, 12)
+#define FWL23URL3_CVID		GENMASK(11, 0)
+
+#define FWL23URLR_L		BIT(31)
+#define FWL23URLR_LSF		BIT(1)
+#define FWL23URLR_LF		BIT(0)
+
+#define FWL23UTIM_TR		BIT(1)
+#define FWL23UTIM_TIOG		BIT(0)
+
 #define RSW_AGEING_CLK_PER_US	0x140
 #define RSW_AGEING_TIME		300
 

-- 
2.43.0