From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A87F301033; Wed, 12 Nov 2025 15:33:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762961622; cv=none; b=eQiLnlAEGdsQgxWhx7cIQOsCGFJf5+xet09Lbj+95AXXEfqEzCNYm1tEARNuCCQyaDXhhJZu9x2H/5jYrn4RUEhj3EK02qwzTgXgA6Jfa2VKYhIXOdvDRq1mHIs6cEpWt6oz/R23v9YJLIBrQDwaOayCOwEprPcpCXg0Vm6ksps= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762961622; c=relaxed/simple; bh=HI3eCi1JvGJlHpKpgnqDyPjCMMeri77ni9tLhmKxALM=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=agp3ymtzYATwkmytolXILttuwfSh8NNbyhwJapAqiP1JgBYQsMqiKRJ99dL5C37tZlr9Rn2XNGXZzt8mf0B1NGJlZ6QN3Col0W1ChzOqgyI1yh95zvTRuMKvppert2jbTDrkpYTpEq9+t0YsZ4WOSsQ3ThKu27TEuoezcXJOA1c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4d66qd2jXGzHnGh0; Wed, 12 Nov 2025 23:33:17 +0800 (CST) Received: from dubpeml100005.china.huawei.com (unknown [7.214.146.113]) by mail.maildlp.com (Postfix) with ESMTPS id A53071402CB; Wed, 12 Nov 2025 23:33:36 +0800 (CST) Received: from localhost (10.203.177.15) by dubpeml100005.china.huawei.com (7.214.146.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Wed, 12 Nov 2025 15:33:35 +0000 Date: Wed, 12 Nov 2025 15:33:34 +0000 From: Jonathan Cameron To: CC: , , , , , , , , , Alejandro Lucero , "Alison Schofield" , Ben Cheatham Subject: Re: [PATCH v20 04/22] cxl: Add type2 device basic support Message-ID: <20251112153334.00000ea2@huawei.com> In-Reply-To: <20251110153657.2706192-5-alejandro.lucero-palau@amd.com> References: <20251110153657.2706192-1-alejandro.lucero-palau@amd.com> <20251110153657.2706192-5-alejandro.lucero-palau@amd.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml500010.china.huawei.com (7.191.174.240) To dubpeml100005.china.huawei.com (7.214.146.113) On Mon, 10 Nov 2025 15:36:39 +0000 alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero > > Differentiate CXL memory expanders (type 3) from CXL device accelerators > (type 2) with a new function for initializing cxl_dev_state and a macro > for helping accel drivers to embed cxl_dev_state inside a private > struct. > > Move structs to include/cxl as the size of the accel driver private > struct embedding cxl_dev_state needs to know the size of this struct. > > Use same new initialization with the type3 pci driver. > > Signed-off-by: Alejandro Lucero > Reviewed-by: Jonathan Cameron > Reviewed-by: Dave Jiang > Reviewed-by: Alison Schofield > Reviewed-by: Ben Cheatham One minor thing that's probably a merge conflict gone slightly wrong or something like that. After this patch you end up with two CXL_NR_PARTITIONS_MAX defines. > --- > drivers/cxl/core/mbox.c | 12 +- > drivers/cxl/core/memdev.c | 32 +++++ > drivers/cxl/core/pci_drv.c | 15 +-- > drivers/cxl/cxl.h | 97 +-------------- > drivers/cxl/cxlmem.h | 85 +------------ > include/cxl/cxl.h | 226 +++++++++++++++++++++++++++++++++++ > tools/testing/cxl/test/mem.c | 3 +- > 7 files changed, 276 insertions(+), 194 deletions(-) > create mode 100644 include/cxl/cxl.h > > diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h > new file mode 100644 > index 000000000000..13d448686189 > --- /dev/null > +++ b/include/cxl/cxl.h > @@ -0,0 +1,226 @@ > +#define CXL_NR_PARTITIONS_MAX 2 Adds a definition but doesn't remove the one in driver/cxl/cxlmem.h That seems odd.