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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Frank Wunderlich , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: Re: [PATCH RFC net-next 0/3] net: dsa: initial support for MaxLinear MxL862xx switches Message-ID: <20251203202605.t4bwihwscc4vkdzz@skbuf> References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Daniel, On Tue, Dec 02, 2025 at 11:37:13PM +0000, Daniel Golle wrote: > Hi, > > This series adds very basic DSA support for the MaxLinear MxL86252 > (5 PHY ports) and MxL86282 (8 PHY ports) switches. The intent is to > validate and get feedback on the overall approach and driver structure, > especially the firmware-mediated host interface. > > MxL862xx integrates a firmware running on an embedded processor (Zephyr > RTOS). Host interaction uses a simple API transported over MDIO/MMD. > This series includes only what's needed to pass traffic between user > ports and the CPU port: relayed MDIO to internal PHYs, basic port > enable/disable, and CPU-port special tagging. > > Thanks for taking a look. I see no phylink_mac_ops in your patches. How does this switch architecture deal with SFP cages? I see the I2C controllers aren't accessible through the MDIO relay protocol implemented by the microcontroller. So I guess using the sfp-bus code isn't going to be possible. The firmware manages the SFP cage and you "just" have to read the USXGMII Status Register (reg 30.19) from the host? How does that work out in practice?