From: Vladimir Oltean <olteanv@gmail.com>
To: Daniel Golle <daniel@makrotopia.org>
Cc: Andrew Lunn <andrew@lunn.ch>, Hauke Mehrtens <hauke@hauke-m.de>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Russell King <linux@armlinux.org.uk>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
Rasmus Villemoes <ravi@prevas.dk>,
"Benny (Ying-Tsan) Weng" <yweng@maxlinear.com>,
John Crispin <john@phrozen.org>
Subject: Re: [PATCH net] net: dsa: mxl-gsw1xx: manually clear RANEG bit
Date: Fri, 5 Dec 2025 16:06:55 +0200 [thread overview]
Message-ID: <20251205140655.mxe32abnagpvjuri@skbuf> (raw)
In-Reply-To: <aTLkl0Zey4u4P8x6@makrotopia.org>
On Fri, Dec 05, 2025 at 01:56:39PM +0000, Daniel Golle wrote:
> On Fri, Dec 05, 2025 at 02:45:35PM +0100, Andrew Lunn wrote:
> > On Fri, Dec 05, 2025 at 01:32:20AM +0000, Daniel Golle wrote:
> > > Despite being documented as self-clearing, the RANEG bit sometimes
> > > remains set, preventing auto-negotiation from happening.
> > >
> > > Manually clear the RANEG bit after 10ms as advised by MaxLinear, using
> > > delayed_work emulating the asynchronous self-clearing behavior.
> >
> > Maybe add some text why the complexity of delayed work is used, rather
> > than just a msleep(10)?
> >
> > Calling regmap_read_poll_timeout() to see if it clears itself could
> > optimise this, and still be simpler.
>
> Is the restart_an() operation allowed to sleep?
Isn't regmap_set_bits() already sleeping? Your gsw1xx_regmap_bus
accesses __mdiobus_write() and __mdiobus_read() which are sleepable
operations and there's no problem with that.
next prev parent reply other threads:[~2025-12-05 14:07 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-05 1:32 [PATCH net] net: dsa: mxl-gsw1xx: manually clear RANEG bit Daniel Golle
2025-12-05 13:45 ` Andrew Lunn
2025-12-05 13:56 ` Daniel Golle
2025-12-05 14:06 ` Andrew Lunn
2025-12-05 14:06 ` Vladimir Oltean [this message]
2025-12-05 15:17 ` Russell King (Oracle)
2025-12-05 15:40 ` Daniel Golle
2025-12-05 15:52 ` Russell King (Oracle)
2025-12-05 19:06 ` Daniel Golle
2025-12-05 15:58 ` Andrew Lunn
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