From: irving.ch.lin <irving-ch.lin@mediatek.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Richard Cochran <richardcochran@gmail.com>
Cc: Qiqi Wang <qiqi.wang@mediatek.com>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <linux-pm@vger.kernel.org>,
<netdev@vger.kernel.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
<sirius.wang@mediatek.com>, <vince-wl.liu@mediatek.com>,
<jh.hsu@mediatek.com>, <irving-ch.lin@mediatek.com>
Subject: [PATCH v4 02/21] dt-bindings: power: mediatek: Add MT8189 power domain definitions
Date: Mon, 15 Dec 2025 11:49:11 +0800 [thread overview]
Message-ID: <20251215034944.2973003-3-irving-ch.lin@mediatek.com> (raw)
In-Reply-To: <20251215034944.2973003-1-irving-ch.lin@mediatek.com>
From: Irving-CH Lin <irving-ch.lin@mediatek.com>
Add device tree bindings for the power domains of MediaTek MT8189 SoC.
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
---
.../power/mediatek,power-controller.yaml | 1 +
.../dt-bindings/power/mediatek,mt8189-power.h | 38 +++++++++++++++++++
2 files changed, 39 insertions(+)
create mode 100644 include/dt-bindings/power/mediatek,mt8189-power.h
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index f8a13928f615..443c227c0e51 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -31,6 +31,7 @@ properties:
- mediatek,mt8183-power-controller
- mediatek,mt8186-power-controller
- mediatek,mt8188-power-controller
+ - mediatek,mt8189-power-controller
- mediatek,mt8192-power-controller
- mediatek,mt8195-power-controller
- mediatek,mt8196-hwv-hfrp-power-controller
diff --git a/include/dt-bindings/power/mediatek,mt8189-power.h b/include/dt-bindings/power/mediatek,mt8189-power.h
new file mode 100644
index 000000000000..70a8c2113457
--- /dev/null
+++ b/include/dt-bindings/power/mediatek,mt8189-power.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Qiqi Wang <qiqi.wang@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8189_POWER_H
+#define _DT_BINDINGS_POWER_MT8189_POWER_H
+
+/* SPM */
+#define MT8189_POWER_DOMAIN_CONN 0
+#define MT8189_POWER_DOMAIN_AUDIO 1
+#define MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT 2
+#define MT8189_POWER_DOMAIN_ADSP_INFRA 3
+#define MT8189_POWER_DOMAIN_ADSP_AO 4
+#define MT8189_POWER_DOMAIN_MM_INFRA 5
+#define MT8189_POWER_DOMAIN_ISP_IMG1 6
+#define MT8189_POWER_DOMAIN_ISP_IMG2 7
+#define MT8189_POWER_DOMAIN_ISP_IPE 8
+#define MT8189_POWER_DOMAIN_VDE0 9
+#define MT8189_POWER_DOMAIN_VEN0 10
+#define MT8189_POWER_DOMAIN_CAM_MAIN 11
+#define MT8189_POWER_DOMAIN_CAM_SUBA 12
+#define MT8189_POWER_DOMAIN_CAM_SUBB 13
+#define MT8189_POWER_DOMAIN_MDP0 14
+#define MT8189_POWER_DOMAIN_DISP 15
+#define MT8189_POWER_DOMAIN_DP_TX 16
+#define MT8189_POWER_DOMAIN_CSI_RX 17
+#define MT8189_POWER_DOMAIN_SSUSB 18
+#define MT8189_POWER_DOMAIN_MFG0 19
+#define MT8189_POWER_DOMAIN_MFG1 20
+#define MT8189_POWER_DOMAIN_MFG2 21
+#define MT8189_POWER_DOMAIN_MFG3 22
+#define MT8189_POWER_DOMAIN_EDP_TX_DORMANT 23
+#define MT8189_POWER_DOMAIN_PCIE 24
+#define MT8189_POWER_DOMAIN_PCIE_PHY 25
+
+#endif /* _DT_BINDINGS_POWER_MT8189_POWER_H */
--
2.45.2
next prev parent reply other threads:[~2025-12-15 3:50 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-15 3:49 [PATCH v4 00/21] Add support for MT8189 clock/power controller irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 01/21] dt-bindings: clock: mediatek: Add MT8189 clock definitions irving.ch.lin
2025-12-19 7:35 ` Krzysztof Kozlowski
2025-12-15 3:49 ` irving.ch.lin [this message]
2025-12-19 7:36 ` [PATCH v4 02/21] dt-bindings: power: mediatek: Add MT8189 power domain definitions Krzysztof Kozlowski
2025-12-19 7:42 ` Krzysztof Kozlowski
2025-12-15 3:49 ` [PATCH v4 03/21] clk: mediatek: clk-mux: Make sure bypass clk enabled while setting MFG rate irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 04/21] clk: mediatek: Add MT8189 apmixedsys clock support irving.ch.lin
2025-12-22 18:00 ` Brian Masney
2025-12-15 3:49 ` [PATCH v4 05/21] clk: mediatek: Add MT8189 topckgen " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 06/21] clk: mediatek: Add MT8189 vlpckgen " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 07/21] clk: mediatek: Add MT8189 vlpcfg " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 08/21] clk: mediatek: Add MT8189 bus " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 09/21] clk: mediatek: Add MT8189 cam " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 10/21] clk: mediatek: Add MT8189 dbgao " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 11/21] clk: mediatek: Add MT8189 dvfsrc " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 12/21] clk: mediatek: Add MT8189 i2c " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 13/21] clk: mediatek: Add MT8189 img " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 14/21] clk: mediatek: Add MT8189 mdp " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 15/21] clk: mediatek: Add MT8189 mfg " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 16/21] clk: mediatek: Add MT8189 dispsys " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 17/21] clk: mediatek: Add MT8189 scp " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 18/21] clk: mediatek: Add MT8189 ufs " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 19/21] clk: mediatek: Add MT8189 vcodec " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 20/21] pmdomain: mediatek: Add bus protect control flow for MT8189 irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 21/21] pmdomain: mediatek: Add power domain driver for MT8189 SoC irving.ch.lin
2025-12-15 15:57 ` [PATCH v4 00/21] Add support for MT8189 clock/power controller Ulf Hansson
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