[PATCH v1 0/2] net: stmmac: eic7700: fix EIC7700 eth1 RX sampling timing

[lizhi2@eswincomputing.com]

From: Zhi Li <lizhi2@eswincomputing.com>

This series addresses an RX data sampling timing issue observed on the
second Ethernet controller (eth1) of the Eswin EIC7700 SoC.

On the EIC7700 SoC, the hardware introduces a receive clock to data skew
on eth1 that is not strictly fixed, but remains within a bounded range
under normal operating conditions. At Gigabit speed, this skew causes
the receive clock edge to occur later than the corresponding RX data at
the MAC input, which can result in incorrect RX data sampling.

The existing internal RX delay mechanisms, including the use of rgmii-id
mode and rx-internal-delay-ps adjustment, provide only a limited amount
of additional delay on the receive path, which does not offer sufficient
adjustment range to compensate for this condition. To address this, the
EIC7700 MAC provides an EIC7700-specific clock sampling inversion control,
which effectively shifts the sampling edge earlier and restores a valid
RX sampling window for Gigabit operation.

In addition, this series updates the enum values of the
rx-internal-delay-ps and tx-internal-delay-ps properties in the device
tree binding to reflect the actual delay step resolution implemented by
the EIC7700 hardware. The hardware applies delay in 20 ps increments,
while the previous enum values were based on an incorrect 100 ps per
step mapping.

The binding enum values and the driver conversion logic are updated
together so that the specified delay in picoseconds maps correctly to
the underlying hardware delay steps. This change corrects the DT-to-
hardware mapping and does not change the meaning or intended usage of
the delay properties.

The first patch updates the device tree binding to describe optional
clock sampling inversion control and the required HSP CSR registers.

The second patch updates the EIC7700 DWMAC glue driver to apply the
sampling correction at Gigabit speed, clear residual delay settings
left by the bootloader, and ensure all register accesses are performed
only after clocks are enabled.

These changes restore reliable RX operation on eth1 and ensure the
hardware is initialized into a known and consistent state.

Zhi Li (2):
  dt-bindings: ethernet: eswin: add clock sampling control
  net: stmmac: eic7700: enable clocks before syscon access and correct
    RX sampling timing

 .../bindings/net/eswin,eic7700-eth.yaml       |  57 +++++++-
 .../ethernet/stmicro/stmmac/dwmac-eic7700.c   | 132 +++++++++++++-----
 2 files changed, 148 insertions(+), 41 deletions(-)

-- 
2.25.1