* [PATCH v3 1/3] net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII
2026-01-13 14:13 [PATCH v3 0/3] s32g: Use a syscon for GPR Dan Carpenter
@ 2026-01-13 14:13 ` Dan Carpenter
2026-01-13 14:13 ` [PATCH v3 2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Dan Carpenter
2026-01-17 17:27 ` [PATCH v3 0/3] s32g: Use a syscon for GPR Jakub Kicinski
2 siblings, 0 replies; 5+ messages in thread
From: Dan Carpenter @ 2026-01-13 14:13 UTC (permalink / raw)
To: Jan Petrous, Frank Li
Cc: s32, Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, netdev,
linux-stm32, linux-arm-kernel, linux-kernel, linaro-s32, imx
On the s32 chipsets the GMAC_0_CTRL_STS register is in GPR region.
Originally, accessing this register was done in a sort of ad-hoc way,
but we want to use the syscon interface to do it.
This is a little bit ugly because we have to maintain backwards
compatibility to the old device trees so we have to support both ways
to access this register.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
---
v3: Unchanged
v2: Fix forward porting bug. s/PHY_INTF_SEL_RGMII/S32_PHY_INTF_SEL_RGMII/
.../net/ethernet/stmicro/stmmac/dwmac-s32.c | 23 +++++++++++++++----
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
index 5a485ee98fa7..2e6bb41f49e1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
@@ -11,12 +11,14 @@
#include <linux/device.h>
#include <linux/ethtool.h>
#include <linux/io.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_mdio.h>
#include <linux/of_address.h>
#include <linux/phy.h>
#include <linux/phylink.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/stmmac.h>
#include "stmmac_platform.h"
@@ -32,6 +34,8 @@
struct s32_priv_data {
void __iomem *ioaddr;
void __iomem *ctrl_sts;
+ struct regmap *sts_regmap;
+ unsigned int sts_offset;
struct device *dev;
phy_interface_t *intf_mode;
struct clk *tx_clk;
@@ -40,7 +44,10 @@ struct s32_priv_data {
static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac)
{
- writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts);
+ if (gmac->ctrl_sts)
+ writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts);
+ else
+ regmap_write(gmac->sts_regmap, gmac->sts_offset, S32_PHY_INTF_SEL_RGMII);
dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode));
@@ -125,10 +132,16 @@ static int s32_dwmac_probe(struct platform_device *pdev)
"dt configuration failed\n");
/* PHY interface mode control reg */
- gmac->ctrl_sts = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
- if (IS_ERR(gmac->ctrl_sts))
- return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts),
- "S32CC config region is missing\n");
+ gmac->sts_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,
+ "nxp,phy-sel", 1, &gmac->sts_offset);
+ if (gmac->sts_regmap == ERR_PTR(-EPROBE_DEFER))
+ return PTR_ERR(gmac->sts_regmap);
+ if (IS_ERR(gmac->sts_regmap)) {
+ gmac->ctrl_sts = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
+ if (IS_ERR(gmac->ctrl_sts))
+ return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts),
+ "S32CC config region is missing\n");
+ }
/* tx clock */
gmac->tx_clk = devm_clk_get(&pdev->dev, "tx");
--
2.51.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v3 2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon
2026-01-13 14:13 [PATCH v3 0/3] s32g: Use a syscon for GPR Dan Carpenter
2026-01-13 14:13 ` [PATCH v3 1/3] net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII Dan Carpenter
@ 2026-01-13 14:13 ` Dan Carpenter
2026-01-16 17:57 ` Rob Herring
2026-01-17 17:27 ` [PATCH v3 0/3] s32g: Use a syscon for GPR Jakub Kicinski
2 siblings, 1 reply; 5+ messages in thread
From: Dan Carpenter @ 2026-01-13 14:13 UTC (permalink / raw)
To: Jan Petrous, Frank Li
Cc: s32, Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
netdev, devicetree, linux-kernel, linaro-s32, imx
The S32 chipsets have a GPR region which has a miscellaneous registers
including the GMAC_0_CTRL_STS register. Originally, this code accessed
that register in a sort of ad-hoc way, but it's cleaner to use a
syscon interface to access these registers.
We still need to maintain the old method of accessing the GMAC register
but using a syscon will let us access other registers more cleanly.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
---
v3: Better documentation about what GMAC_0_CTRL_STS register does.
v2: Add the vendor prefix to the phandle
Fix the documentation
.../devicetree/bindings/net/nxp,s32-dwmac.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
index 2b8b74c5feec..cc0dd3941715 100644
--- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
@@ -32,6 +32,17 @@ properties:
- description: Main GMAC registers
- description: GMAC PHY mode control register
+ nxp,phy-sel:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - description: phandle to the GPR syscon node
+ - description: offset of PHY selection register
+ description:
+ This phandle points to the GMAC_0_CTRL_STS register which controls the
+ GMAC_0 configuration options. The register lets you select the PHY
+ interface and the PHY mode. It also controls if the FTM_0 or FTM_1
+ FlexTimer Modules connect to GMAC_O.
+
interrupts:
maxItems: 1
@@ -74,6 +85,7 @@ examples:
compatible = "nxp,s32g2-dwmac";
reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
<0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
+ nxp,phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
--
2.51.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v3 2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon
2026-01-13 14:13 ` [PATCH v3 2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Dan Carpenter
@ 2026-01-16 17:57 ` Rob Herring
0 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2026-01-16 17:57 UTC (permalink / raw)
To: Dan Carpenter
Cc: Jan Petrous, Frank Li, s32, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Krzysztof Kozlowski,
Conor Dooley, netdev, devicetree, linux-kernel, linaro-s32, imx
On Tue, Jan 13, 2026 at 05:13:32PM +0300, Dan Carpenter wrote:
> The S32 chipsets have a GPR region which has a miscellaneous registers
> including the GMAC_0_CTRL_STS register. Originally, this code accessed
> that register in a sort of ad-hoc way, but it's cleaner to use a
> syscon interface to access these registers.
>
> We still need to maintain the old method of accessing the GMAC register
> but using a syscon will let us access other registers more cleanly.
>
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
> ---
> v3: Better documentation about what GMAC_0_CTRL_STS register does.
> v2: Add the vendor prefix to the phandle
> Fix the documentation
>
> .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> index 2b8b74c5feec..cc0dd3941715 100644
> --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> @@ -32,6 +32,17 @@ properties:
> - description: Main GMAC registers
> - description: GMAC PHY mode control register
>
> + nxp,phy-sel:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - description: phandle to the GPR syscon node
> + - description: offset of PHY selection register
It should be:
items:
- items:
- description: ...
- description: ...
Because it is 1 phandle+args entry of 2 cells.
Rob
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3 0/3] s32g: Use a syscon for GPR
2026-01-13 14:13 [PATCH v3 0/3] s32g: Use a syscon for GPR Dan Carpenter
2026-01-13 14:13 ` [PATCH v3 1/3] net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII Dan Carpenter
2026-01-13 14:13 ` [PATCH v3 2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Dan Carpenter
@ 2026-01-17 17:27 ` Jakub Kicinski
2 siblings, 0 replies; 5+ messages in thread
From: Jakub Kicinski @ 2026-01-17 17:27 UTC (permalink / raw)
To: Dan Carpenter
Cc: Chester Lin, Frank Li, Alexandre Torgue, Andrew Lunn,
Conor Dooley, David S. Miller, devicetree, Eric Dumazet,
Fabio Estevam, Ghennadi Procopciuc, imx, Jan Petrous,
Krzysztof Kozlowski, linux-arm-kernel, linux-kernel, linux-stm32,
Matthias Brugger, Maxime Coquelin, netdev, NXP S32 Linux Team,
Paolo Abeni, Pengutronix Kernel Team, Rob Herring, Sascha Hauer,
Shawn Guo, linaro-s32
On Tue, 13 Jan 2026 17:13:23 +0300 Dan Carpenter wrote:
> Dan Carpenter (3):
> net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII
> dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon
> dts: s32g: Add GPR syscon region
For v4 could you CC netdev on all 3? Even tho we won't apply patch 3
if patchwork sees just a subset of the series it won't kick off our CI.
^ permalink raw reply [flat|nested] 5+ messages in thread