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From: Ivan Vecera <ivecera@redhat.com>
To: netdev@vger.kernel.org
Cc: Alexander Lobakin <aleksander.lobakin@intel.com>,
	Andrew Lunn <andrew+netdev@lunn.ch>,
	Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
	Conor Dooley <conor+dt@kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Grzegorz Nitka <grzegorz.nitka@intel.com>,
	Jakub Kicinski <kuba@kernel.org>, Jiri Pirko <jiri@resnulli.us>,
	Jonathan Lemon <jonathan.lemon@gmail.com>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Leon Romanovsky <leon@kernel.org>, Mark Bloch <mbloch@nvidia.com>,
	Michal Schmidt <mschmidt@redhat.com>,
	Paolo Abeni <pabeni@redhat.com>, Petr Oros <poros@redhat.com>,
	Prathosh Satish <Prathosh.Satish@microchip.com>,
	Przemek Kitszel <przemyslaw.kitszel@intel.com>,
	Richard Cochran <richardcochran@gmail.com>,
	Rob Herring <robh@kernel.org>, Saeed Mahameed <saeedm@nvidia.com>,
	Saravana Kannan <saravanak@kernel.org>,
	Tariq Toukan <tariqt@nvidia.com>,
	Tony Nguyen <anthony.l.nguyen@intel.com>,
	Vadim Fedorenko <vadim.fedorenko@linux.dev>,
	devicetree@vger.kernel.org, intel-wired-lan@lists.osuosl.org,
	linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org
Subject: [PATCH net-next v2 01/12] dt-bindings: dpll: support acting as pin provider
Date: Fri, 16 Jan 2026 19:45:59 +0100	[thread overview]
Message-ID: <20260116184610.147591-2-ivecera@redhat.com> (raw)
In-Reply-To: <20260116184610.147591-1-ivecera@redhat.com>

Enable DPLL devices to act as pin providers for consumers (such as
Ethernet controllers or PHYs).

Add the '#dpll-pin-cells' property to the generic dpll-device.yaml
schema and mark it as required. This allows DPLL nodes to define pin
specifiers for their connected consumers.

Introduce a new header '<dt-bindings/dpll/dpll.h>' to define pin
direction macros (`DPLL_PIN_INPUT` and `DPLL_PIN_OUTPUT`). These macros
are intended to be used in the DT pin specifiers (inside 'dpll-pins'
properties of consumers) to describe the direction of the signal.

Update the 'microchip,zl30731.yaml' examples to include the new
'#dpll-pin-cells' property.

The core schema definitions for these properties are being added to
dt-schema in PR #183.

Link: https://github.com/devicetree-org/dt-schema/pull/183
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
---
v2:
* removed dpll-pin-consumer.yaml schema per request
* added '#dpll-pin-cells' property into dpll-device.yaml and
  microchip,zl30731.yaml
---
 .../devicetree/bindings/dpll/dpll-device.yaml       | 10 ++++++++++
 .../devicetree/bindings/dpll/microchip,zl30731.yaml |  4 ++++
 MAINTAINERS                                         |  1 +
 include/dt-bindings/dpll/dpll.h                     | 13 +++++++++++++
 4 files changed, 28 insertions(+)
 create mode 100644 include/dt-bindings/dpll/dpll.h

diff --git a/Documentation/devicetree/bindings/dpll/dpll-device.yaml b/Documentation/devicetree/bindings/dpll/dpll-device.yaml
index fb8d7a9a3693f..5022cbd77f308 100644
--- a/Documentation/devicetree/bindings/dpll/dpll-device.yaml
+++ b/Documentation/devicetree/bindings/dpll/dpll-device.yaml
@@ -27,6 +27,13 @@ properties:
   "#size-cells":
     const: 0
 
+  "#dpll-pin-cells":
+    const: 2
+    description: |
+      - Specified pin index
+      - Specified pin direction. The macros are defined in
+        dt-bindings/dpll/dpll.h
+
   dpll-types:
     description: List of DPLL channel types, one per DPLL instance.
     $ref: /schemas/types.yaml#/definitions/non-unique-string-array
@@ -73,4 +80,7 @@ properties:
       - "#address-cells"
       - "#size-cells"
 
+required:
+  - "#dpll-pin-cells"
+
 additionalProperties: true
diff --git a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
index 17747f754b845..6693151af6ccb 100644
--- a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
+++ b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
@@ -44,6 +44,8 @@ examples:
       #size-cells = <0>;
 
       dpll@70 {
+        #dpll-pin-cells = <2>;
+
         compatible = "microchip,zl30732";
         reg = <0x70>;
         dpll-types = "pps", "eec";
@@ -80,6 +82,8 @@ examples:
       #size-cells = <0>;
 
       dpll@70 {
+        #dpll-pin-cells = <2>;
+
         compatible = "microchip,zl30731";
         reg = <0x70>;
         spi-max-frequency = <12500000>;
diff --git a/MAINTAINERS b/MAINTAINERS
index afc71089ba09f..d359d42f64223 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7655,6 +7655,7 @@ F:	Documentation/devicetree/bindings/dpll/dpll-device.yaml
 F:	Documentation/devicetree/bindings/dpll/dpll-pin.yaml
 F:	Documentation/driver-api/dpll.rst
 F:	drivers/dpll/
+F:	include/dt-bindings/dpll/dpll.h
 F:	include/linux/dpll.h
 F:	include/uapi/linux/dpll.h
 
diff --git a/include/dt-bindings/dpll/dpll.h b/include/dt-bindings/dpll/dpll.h
new file mode 100644
index 0000000000000..5fc9815800fc0
--- /dev/null
+++ b/include/dt-bindings/dpll/dpll.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
+/*
+ * This header provides constants for DPLL bindings.
+ */
+
+#ifndef _DT_BINDINGS_DPLL_DPLL_H
+#define _DT_BINDINGS_DPLL_DPLL_H
+
+/* DPLL pin direction */
+#define DPLL_PIN_INPUT 0
+#define DPLL_PIN_OUTPUT 1
+
+#endif
-- 
2.52.0


  reply	other threads:[~2026-01-16 18:46 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-16 18:45 [PATCH net-next v2 00/12] dpll: Core improvements and ice E825-C SyncE support Ivan Vecera
2026-01-16 18:45 ` Ivan Vecera [this message]
2026-01-16 18:46 ` [PATCH net-next v2 02/12] dpll: Allow associating dpll pin with a firmware node Ivan Vecera
2026-01-16 18:46 ` [PATCH net-next v2 03/12] dpll: Add helpers to find DPLL pin fwnode Ivan Vecera
2026-02-08  1:46   ` Saravana Kannan
2026-02-10  7:19   ` [Intel-wired-lan] " Loktionov, Aleksandr
2026-01-16 18:46 ` [PATCH net-next v2 04/12] dpll: zl3073x: Associate pin with fwnode handle Ivan Vecera
2026-01-19  7:49   ` [Intel-wired-lan] " Loktionov, Aleksandr
2026-01-16 18:46 ` [PATCH net-next v2 05/12] dpll: Add notifier chain for dpll events Ivan Vecera
2026-01-16 18:46 ` [PATCH net-next v2 06/12] dpll: Support dynamic pin index allocation Ivan Vecera
2026-01-16 18:46 ` [PATCH net-next v2 07/12] dpll: zl3073x: Add support for mux pin type Ivan Vecera
2026-01-19  7:50   ` [Intel-wired-lan] " Loktionov, Aleksandr
2026-01-16 18:46 ` [PATCH net-next v2 08/12] dpll: Enhance and consolidate reference counting logic Ivan Vecera
2026-01-21  0:16   ` [net-next,v2,08/12] " Jakub Kicinski
2026-01-21  8:18     ` Ivan Vecera
2026-01-23 14:58       ` Simon Horman
2026-01-23 15:27         ` Ivan Vecera
2026-01-23 18:04           ` Simon Horman
2026-01-16 18:46 ` [PATCH net-next v2 09/12] dpll: Prevent duplicate registrations Ivan Vecera
2026-01-19  7:50   ` [Intel-wired-lan] " Loktionov, Aleksandr
2026-01-16 18:46 ` [PATCH net-next v2 10/12] dpll: Add reference count tracking support Ivan Vecera
2026-01-16 18:46 ` [PATCH net-next v2 11/12] drivers: Add support for DPLL reference count tracking Ivan Vecera
2026-01-16 18:46 ` [PATCH net-next v2 12/12] ice: dpll: Support E825-C SyncE and dynamic pin discovery Ivan Vecera
2026-01-21  0:18   ` [net-next,v2,12/12] " Jakub Kicinski
2026-01-21 14:20     ` Nitka, Grzegorz

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