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Wed, 21 Jan 2026 07:15:24 -0800 (PST) Received: from nas.local ([2001:912:1ac0:1e00:c662:37ff:fe09:93df]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435924ae6f1sm10534349f8f.33.2026.01.21.07.15.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jan 2026 07:15:24 -0800 (PST) From: Damien Dejean To: andrew@lunn.ch, krzk+dt@kernel.org Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, edumazet@google.com, davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, hkallweit1@gmail.com, Damien Dejean Subject: [PATCH v2 4/4] net: phy: realtek: add RTL8224 polarity support Date: Wed, 21 Jan 2026 16:15:06 +0100 Message-ID: <20260121151506.813783-4-dam.dejean@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260121151506.813783-1-dam.dejean@gmail.com> References: <20260121151506.813783-1-dam.dejean@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The RTL8224 has a register to configure the polarity of every pair of each port. It provides device designers more flexbility when wiring the chip. Unfortunately, the register is left in an unknown state after a reset. Thus on devices where the bootloader don't initialize it, the driver has to do it to detect and use a link. The MDI polarity swap can be set in the device tree using the property realtek,mdi-cfg-polarity. The u32 value is a bitfield where bit[0..3] control the polarity of pairs A..D. Signed-off-by: Damien Dejean --- drivers/net/phy/realtek/realtek_main.c | 39 +++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c index 85b0eea936e4..d2dc4f7a1971 100644 --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c @@ -164,6 +164,7 @@ #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) #define RTL8224_VND1_MDI_PAIR_SWAP 0xa90 +#define RTL8224_VND1_MDI_POLARITY_SWAP 0xa94 #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) @@ -1719,9 +1720,45 @@ static int rtl8224_mdi_config_order(struct phy_device *phydev) RTL8224_VND1_MDI_PAIR_SWAP, val); } +static int rtl8224_mdi_config_polarity(struct phy_device *phydev) +{ + struct device_node *np = phydev->mdio.dev.of_node; + u8 port_offset = phydev->mdio.addr & 3; + u32 polarity, val; + int ret; + + ret = of_property_read_u32(np, "realtek,mdi-cfg-polarity", &polarity); + + /* Do nothing if the property is not present */ + if (ret == -EINVAL) + return 0; + + if (!ret) + return ret; + + if (polarity & ~0xf) + return -EINVAL; + + val = __phy_package_read_mmd(phydev, 0, MDIO_MMD_VEND1, + RTL8224_VND1_MDI_POLARITY_SWAP); + if (val < 0) + return val; + + val &= ~(0xf << port_offset); + val |= polarity << port_offset; + return __phy_package_write_mmd(phydev, 0, MDIO_MMD_VEND1, + RTL8224_VND1_MDI_POLARITY_SWAP, val); +} + static int rtl8224_config_init(struct phy_device *phydev) { - return rtl8224_mdi_config_order(phydev); + int ret; + + ret = rtl8224_mdi_config_order(phydev); + if (!ret) + return ret; + + return rtl8224_mdi_config_polarity(phydev); } static int rtl8224_probe(struct phy_device *phydev) -- 2.47.3