* [PATCH net-next v9 1/3] dt-bindings: net: nuvoton: Add schema for Nuvoton MA35 family GMAC
2026-01-26 10:22 [PATCH net-next v9 0/3] Add support for Nuvoton MA35D1 GMAC Joey Lu
@ 2026-01-26 10:22 ` Joey Lu
2026-01-26 10:22 ` [PATCH net-next v9 2/3] arm64: dts: nuvoton: Add Ethernet nodes Joey Lu
2026-01-26 10:22 ` [PATCH net-next v9 3/3] net: stmmac: dwmac-nuvoton: Add dwmac glue for Nuvoton MA35 family Joey Lu
2 siblings, 0 replies; 5+ messages in thread
From: Joey Lu @ 2026-01-26 10:22 UTC (permalink / raw)
To: andrew+netdev, davem, edumazet, kuba, pabeni, robh, krzk+dt,
conor+dt, mcoquelin.stm32, richardcochran
Cc: alexandre.torgue, joabreu, ychuang3, schung, yclu4,
peppe.cavallaro, linux-arm-kernel, netdev, devicetree,
linux-kernel, openbmc, linux-stm32, Joey Lu
Create initial schema for Nuvoton MA35 family Gigabit MAC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Joey Lu <a0987203069@gmail.com>
---
.../bindings/net/nuvoton,ma35d1-dwmac.yaml | 126 ++++++++++++++++++
.../devicetree/bindings/net/snps,dwmac.yaml | 1 +
2 files changed, 127 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml
diff --git a/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml b/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml
new file mode 100644
index 000000000000..8eaddfdc937c
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/nuvoton,ma35d1-dwmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton DWMAC glue layer controller
+
+maintainers:
+ - Joey Lu <yclu4@nuvoton.com>
+
+description:
+ Nuvoton 10/100/1000Mbps Gigabit Ethernet MAC Controller is based on
+ Synopsys DesignWare MAC (version 3.73a).
+
+allOf:
+ - $ref: snps,dwmac.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - nuvoton,ma35d1-dwmac
+
+ reg:
+ maxItems: 1
+ description:
+ Register range should be one of the GMAC interface.
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: MAC clock
+ - description: PTP clock
+
+ clock-names:
+ items:
+ - const: stmmaceth
+ - const: ptp_ref
+
+ nuvoton,sys:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to access syscon registers.
+ - description: GMAC interface ID.
+ enum:
+ - 0
+ - 1
+ description:
+ A phandle to the syscon with one argument that configures system registers
+ for MA35D1's two GMACs. The argument specifies the GMAC interface ID.
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: stmmaceth
+
+ phy-mode:
+ enum:
+ - rmii
+ - rgmii
+ - rgmii-id
+ - rgmii-txid
+ - rgmii-rxid
+
+ tx-internal-delay-ps:
+ default: 0
+ minimum: 0
+ maximum: 2000
+ description:
+ RGMII TX path delay used only when PHY operates in RGMII mode with
+ internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
+ Allowed values are from 0 to 2000.
+
+ rx-internal-delay-ps:
+ default: 0
+ minimum: 0
+ maximum: 2000
+ description:
+ RGMII RX path delay used only when PHY operates in RGMII mode with
+ internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
+ Allowed values are from 0 to 2000.
+
+required:
+ - clocks
+ - clock-names
+ - nuvoton,sys
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+ #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
+ ethernet@40120000 {
+ compatible = "nuvoton,ma35d1-dwmac";
+ reg = <0x40120000 0x10000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk EMAC0_GATE>, <&clk EPLL_DIV8>;
+ clock-names = "stmmaceth", "ptp_ref";
+
+ nuvoton,sys = <&sys 0>;
+ resets = <&sys MA35D1_RESET_GMAC0>;
+ reset-names = "stmmaceth";
+
+ phy-mode = "rgmii-id";
+ phy-handle = <ð_phy0>;
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index dd3c72e8363e..10cb5e555750 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -69,6 +69,7 @@ properties:
- ingenic,x2000-mac
- loongson,ls2k-dwmac
- loongson,ls7a-dwmac
+ - nuvoton,ma35d1-dwmac
- nxp,s32g2-dwmac
- qcom,qcs404-ethqos
- qcom,sa8775p-ethqos
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH net-next v9 2/3] arm64: dts: nuvoton: Add Ethernet nodes
2026-01-26 10:22 [PATCH net-next v9 0/3] Add support for Nuvoton MA35D1 GMAC Joey Lu
2026-01-26 10:22 ` [PATCH net-next v9 1/3] dt-bindings: net: nuvoton: Add schema for Nuvoton MA35 family GMAC Joey Lu
@ 2026-01-26 10:22 ` Joey Lu
2026-01-26 16:17 ` Andrew Lunn
2026-01-26 10:22 ` [PATCH net-next v9 3/3] net: stmmac: dwmac-nuvoton: Add dwmac glue for Nuvoton MA35 family Joey Lu
2 siblings, 1 reply; 5+ messages in thread
From: Joey Lu @ 2026-01-26 10:22 UTC (permalink / raw)
To: andrew+netdev, davem, edumazet, kuba, pabeni, robh, krzk+dt,
conor+dt, mcoquelin.stm32, richardcochran
Cc: alexandre.torgue, joabreu, ychuang3, schung, yclu4,
peppe.cavallaro, linux-arm-kernel, netdev, devicetree,
linux-kernel, openbmc, linux-stm32, Joey Lu
Add GMAC nodes for our MA35D1 development boards:
two RGMII interfaces for SOM board, and one RGMII
and one RMII interface for IoT board.
Signed-off-by: Joey Lu <a0987203069@gmail.com>
---
.../boot/dts/nuvoton/ma35d1-iot-512m.dts | 33 +++++++++++++++++++
.../boot/dts/nuvoton/ma35d1-som-256m.dts | 32 ++++++++++++++++++
arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 32 ++++++++++++++++++
3 files changed, 97 insertions(+)
diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
index 9482bec1aa57..ee32cedf3d9b 100644
--- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
@@ -18,6 +18,8 @@ aliases {
serial12 = &uart12;
serial13 = &uart13;
serial14 = &uart14;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
};
chosen {
@@ -126,3 +128,34 @@ &uart14 {
pinctrl-0 = <&pinctrl_uart14>;
status = "okay";
};
+
+&gmac0 {
+ phy-handle = <ð_phy0>;
+ status = "okay";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gmac1 {
+ phy-mode = "rmii";
+ phy-handle = <ð_phy1>;
+ status = "okay";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
index f6f20a17e501..b1b3e45280d5 100644
--- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
@@ -18,6 +18,8 @@ aliases {
serial12 = &uart12;
serial14 = &uart14;
serial16 = &uart16;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
};
chosen {
@@ -129,3 +131,33 @@ &uart16 {
pinctrl-0 = <&pinctrl_uart16>;
status = "okay";
};
+
+&gmac0 {
+ phy-handle = <ð_phy0>;
+ status = "okay";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gmac1 {
+ phy-handle = <ð_phy1>;
+ status = "okay";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
index e51b98f5bdce..477515ba9a80 100644
--- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
@@ -379,5 +379,37 @@ uart16: serial@40880000 {
clocks = <&clk UART16_GATE>;
status = "disabled";
};
+
+ gmac0: ethernet@40120000 {
+ compatible = "nuvoton,ma35d1-dwmac";
+ reg = <0x0 0x40120000 0x0 0x10000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk EMAC0_GATE>, <&clk EPLL_DIV8>;
+ clock-names = "stmmaceth", "ptp_ref";
+
+ nuvoton,sys = <&sys 0>;
+ resets = <&sys MA35D1_RESET_GMAC0>;
+ reset-names = "stmmaceth";
+
+ phy-mode = "rgmii-id";
+ status = "disabled";
+ };
+
+ gmac1: ethernet@40130000 {
+ compatible = "nuvoton,ma35d1-dwmac";
+ reg = <0x0 0x40130000 0x0 0x10000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk EMAC1_GATE>, <&clk EPLL_DIV8>;
+ clock-names = "stmmaceth", "ptp_ref";
+
+ nuvoton,sys = <&sys 1>;
+ resets = <&sys MA35D1_RESET_GMAC1>;
+ reset-names = "stmmaceth";
+
+ phy-mode = "rgmii-id";
+ status = "disabled";
+ };
};
};
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH net-next v9 2/3] arm64: dts: nuvoton: Add Ethernet nodes
2026-01-26 10:22 ` [PATCH net-next v9 2/3] arm64: dts: nuvoton: Add Ethernet nodes Joey Lu
@ 2026-01-26 16:17 ` Andrew Lunn
0 siblings, 0 replies; 5+ messages in thread
From: Andrew Lunn @ 2026-01-26 16:17 UTC (permalink / raw)
To: Joey Lu
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, robh, krzk+dt,
conor+dt, mcoquelin.stm32, richardcochran, alexandre.torgue,
joabreu, ychuang3, schung, yclu4, peppe.cavallaro,
linux-arm-kernel, netdev, devicetree, linux-kernel, openbmc,
linux-stm32
On Mon, Jan 26, 2026 at 06:22:56PM +0800, Joey Lu wrote:
> Add GMAC nodes for our MA35D1 development boards:
> two RGMII interfaces for SOM board, and one RGMII
> and one RMII interface for IoT board.
>
> Signed-off-by: Joey Lu <a0987203069@gmail.com>
> ---
> .../boot/dts/nuvoton/ma35d1-iot-512m.dts | 33 +++++++++++++++++++
> .../boot/dts/nuvoton/ma35d1-som-256m.dts | 32 ++++++++++++++++++
> arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 32 ++++++++++++++++++
Did you answer my question about what these represent?
I _think_ your .dts{i} files are all messed up and need
re-architecturing.
arch/arm64/boot/dts/nuvoton/ma35d1.dtsi should represent the SoC.
There should be a .dtsi file which represents everything on the SOM.
This includes the SoC .dtsi file.
There should be a .dts file for the carrier board. It should include
the SOM .dtsi file.
You said one of the boards does not use the SOM, so it can directly
import the SoC .dtsi file.
> 3 files changed, 97 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
> index 9482bec1aa57..ee32cedf3d9b 100644
> --- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
> @@ -18,6 +18,8 @@ aliases {
> serial12 = &uart12;
> serial13 = &uart13;
> serial14 = &uart14;
> + ethernet0 = &gmac0;
> + ethernet1 = &gmac1;
> };
>
> chosen {
> @@ -126,3 +128,34 @@ &uart14 {
> pinctrl-0 = <&pinctrl_uart14>;
> status = "okay";
> };
> +
> +&gmac0 {
> + phy-handle = <ð_phy0>;
This is a .dts file, so represents a board. You said the PHYs are on
the board, not the SOM. So this is correct.
> + status = "okay";
> +
> + mdio0: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
The MDIO bus is a property of the SoC. It always exists, even if it is
not used. So the mdio node should be in the SoC .dtsi file.
> + eth_phy0: ethernet-phy@0 {
> + reg = <0>;
> + };
The PHY is a property of the board, so should be in the board .dts
file.
> + };
> +};
> +
> +&gmac1 {
> + phy-mode = "rmii";
> + phy-handle = <ð_phy1>;
> + status = "okay";
Correct.
> +
> + mdio1: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
Wrong.
> +
> + eth_phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
Correct.
> + };
> +};
> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
> index f6f20a17e501..b1b3e45280d5 100644
> --- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
> @@ -18,6 +18,8 @@ aliases {
> serial12 = &uart12;
> serial14 = &uart14;
> serial16 = &uart16;
> + ethernet0 = &gmac0;
> + ethernet1 = &gmac1;
> };
>
> chosen {
> @@ -129,3 +131,33 @@ &uart16 {
> pinctrl-0 = <&pinctrl_uart16>;
> status = "okay";
> };
> +
> +&gmac0 {
> + phy-handle = <ð_phy0>;
> + status = "okay";
> +
> + mdio0: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + eth_phy0: ethernet-phy@0 {
> + reg = <0>;
> + };
> + };
> +};
> +
> +&gmac1 {
> + phy-handle = <ð_phy1>;
> + status = "okay";
> +
> + mdio1: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + eth_phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> + };
> +};
Same problem as above.
> --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
This represents the SoC.
> @@ -379,5 +379,37 @@ uart16: serial@40880000 {
> clocks = <&clk UART16_GATE>;
> status = "disabled";
> };
> +
> + gmac0: ethernet@40120000 {
> + compatible = "nuvoton,ma35d1-dwmac";
> + reg = <0x0 0x40120000 0x0 0x10000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&clk EMAC0_GATE>, <&clk EPLL_DIV8>;
> + clock-names = "stmmaceth", "ptp_ref";
> +
> + nuvoton,sys = <&sys 0>;
> + resets = <&sys MA35D1_RESET_GMAC0>;
> + reset-names = "stmmaceth";
> +
> + phy-mode = "rgmii-id";
PHY mode is a property of the board. The board might have extra long
clock lines, so needs 'rgmii'. The board might use MII?
Please think about the hierarchy. SoC -> SoM -> board. Put the
properties at the correct level.
Andrew
---
pw-bot: cr
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH net-next v9 3/3] net: stmmac: dwmac-nuvoton: Add dwmac glue for Nuvoton MA35 family
2026-01-26 10:22 [PATCH net-next v9 0/3] Add support for Nuvoton MA35D1 GMAC Joey Lu
2026-01-26 10:22 ` [PATCH net-next v9 1/3] dt-bindings: net: nuvoton: Add schema for Nuvoton MA35 family GMAC Joey Lu
2026-01-26 10:22 ` [PATCH net-next v9 2/3] arm64: dts: nuvoton: Add Ethernet nodes Joey Lu
@ 2026-01-26 10:22 ` Joey Lu
2 siblings, 0 replies; 5+ messages in thread
From: Joey Lu @ 2026-01-26 10:22 UTC (permalink / raw)
To: andrew+netdev, davem, edumazet, kuba, pabeni, robh, krzk+dt,
conor+dt, mcoquelin.stm32, richardcochran
Cc: alexandre.torgue, joabreu, ychuang3, schung, yclu4,
peppe.cavallaro, linux-arm-kernel, netdev, devicetree,
linux-kernel, openbmc, linux-stm32, Joey Lu, Andrew Lunn
Add support for Gigabit Ethernet on Nuvoton MA35 series using dwmac driver.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Joey Lu <a0987203069@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
.../ethernet/stmicro/stmmac/dwmac-nuvoton.c | 174 ++++++++++++++++++
3 files changed, 187 insertions(+)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-nuvoton.c
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 07088d03dbab..861f1c6c14f1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -132,6 +132,18 @@ config DWMAC_MESON
the stmmac device driver. This driver is used for Meson6,
Meson8, Meson8b and GXBB SoCs.
+config DWMAC_NUVOTON
+ tristate "Nuvoton MA35 dwmac support"
+ default ARCH_MA35
+ depends on OF && (ARCH_MA35 || COMPILE_TEST)
+ select MFD_SYSCON
+ help
+ Support for Ethernet controller on Nuvoton MA35 series SoC.
+
+ This selects the Nuvoton MA35 series SoC glue layer support
+ for the stmmac device driver. The nuvoton-dwmac driver is
+ used for MA35 series SoCs.
+
config DWMAC_QCOM_ETHQOS
tristate "Qualcomm ETHQOS support"
default ARCH_QCOM
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index c9263987ef8d..4ade030b634f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o
obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o
obj-$(CONFIG_DWMAC_MEDIATEK) += dwmac-mediatek.o
obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o
+obj-$(CONFIG_DWMAC_NUVOTON) += dwmac-nuvoton.o
obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o
obj-$(CONFIG_DWMAC_RENESAS_GBETH) += dwmac-renesas-gbeth.o
obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-nuvoton.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-nuvoton.c
new file mode 100644
index 000000000000..728f5f453515
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-nuvoton.c
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Nuvoton DWMAC specific glue layer
+ *
+ * Copyright (C) 2025 Nuvoton Technology Corp.
+ *
+ * Author: Joey Lu <a0987203069@gmail.com>
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/of_net.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/stmmac.h>
+
+#include "stmmac.h"
+#include "stmmac_platform.h"
+
+#define NVT_REG_SYS_GMAC0MISCR 0x108
+#define NVT_REG_SYS_GMAC1MISCR 0x10C
+
+#define NVT_MISCR_RMII BIT(0)
+
+/* Two thousand picoseconds are evenly mapped to a 4-bit field,
+ * resulting in each step being 2000/15 picoseconds.
+ */
+#define NVT_PATH_DELAY_STEP 134
+#define NVT_TX_DELAY_MASK GENMASK(19, 16)
+#define NVT_RX_DELAY_MASK GENMASK(23, 20)
+
+struct nvt_priv_data {
+ struct platform_device *pdev;
+ struct regmap *regmap;
+};
+
+static struct nvt_priv_data *
+nvt_gmac_setup(struct platform_device *pdev, struct plat_stmmacenet_data *plat)
+{
+ struct device *dev = &pdev->dev;
+ struct nvt_priv_data *bsp_priv;
+ phy_interface_t phy_mode;
+ u32 macid, arg, reg;
+ u32 tx_delay_step;
+ u32 rx_delay_step;
+ u32 miscr;
+
+ bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
+ if (!bsp_priv)
+ return ERR_PTR(-ENOMEM);
+
+ bsp_priv->regmap =
+ syscon_regmap_lookup_by_phandle_args(dev->of_node, "nuvoton,sys", 1, &macid);
+ if (IS_ERR(bsp_priv->regmap)) {
+ dev_err_probe(dev, PTR_ERR(bsp_priv->regmap), "Failed to get sys register\n");
+ return ERR_PTR(-ENODEV);
+ }
+ if (macid > 1) {
+ dev_err_probe(dev, -EINVAL, "Invalid sys arguments\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (of_property_read_u32(dev->of_node, "tx-internal-delay-ps", &arg)) {
+ tx_delay_step = 0;
+ } else {
+ if (arg <= 2000) {
+ tx_delay_step = (arg == 2000) ? 0xf : (arg / NVT_PATH_DELAY_STEP);
+ dev_dbg(dev, "Set Tx path delay to 0x%x\n", tx_delay_step);
+ } else {
+ dev_err(dev, "Invalid Tx path delay argument.\n");
+ return ERR_PTR(-EINVAL);
+ }
+ }
+ if (of_property_read_u32(dev->of_node, "rx-internal-delay-ps", &arg)) {
+ rx_delay_step = 0;
+ } else {
+ if (arg <= 2000) {
+ rx_delay_step = (arg == 2000) ? 0xf : (arg / NVT_PATH_DELAY_STEP);
+ dev_dbg(dev, "Set Rx path delay to 0x%x\n", rx_delay_step);
+ } else {
+ dev_err(dev, "Invalid Rx path delay argument.\n");
+ return ERR_PTR(-EINVAL);
+ }
+ }
+
+ miscr = (macid == 0) ? NVT_REG_SYS_GMAC0MISCR : NVT_REG_SYS_GMAC1MISCR;
+ regmap_read(bsp_priv->regmap, miscr, ®);
+ reg &= ~(NVT_TX_DELAY_MASK | NVT_RX_DELAY_MASK);
+
+ if (of_get_phy_mode(pdev->dev.of_node, &phy_mode)) {
+ dev_err(dev, "missing phy mode property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ switch (phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ reg &= ~NVT_MISCR_RMII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ reg |= NVT_MISCR_RMII;
+ break;
+ default:
+ dev_err(dev, "Unsupported phy-mode (%d)\n", phy_mode);
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (!(reg & NVT_MISCR_RMII)) {
+ reg |= FIELD_PREP(NVT_TX_DELAY_MASK, tx_delay_step);
+ reg |= FIELD_PREP(NVT_RX_DELAY_MASK, rx_delay_step);
+ }
+
+ regmap_write(bsp_priv->regmap, miscr, reg);
+
+ bsp_priv->pdev = pdev;
+
+ return bsp_priv;
+}
+
+static int nvt_gmac_probe(struct platform_device *pdev)
+{
+ struct plat_stmmacenet_data *plat_dat;
+ struct stmmac_resources stmmac_res;
+ struct nvt_priv_data *priv_data;
+ int ret;
+
+ ret = stmmac_get_platform_resources(pdev, &stmmac_res);
+ if (ret)
+ return ret;
+
+ plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
+ if (IS_ERR(plat_dat))
+ return PTR_ERR(plat_dat);
+
+ /* Nuvoton DWMAC configs */
+ plat_dat->core_type = DWMAC_CORE_GMAC;
+ plat_dat->tx_fifo_size = 2048;
+ plat_dat->rx_fifo_size = 4096;
+ plat_dat->multicast_filter_bins = 0;
+ plat_dat->unicast_filter_entries = 8;
+
+ priv_data = nvt_gmac_setup(pdev, plat_dat);
+ if (IS_ERR(priv_data))
+ return PTR_ERR(priv_data);
+
+ ret = stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct of_device_id nvt_dwmac_match[] = {
+ { .compatible = "nuvoton,ma35d1-dwmac"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, nvt_dwmac_match);
+
+static struct platform_driver nvt_dwmac_driver = {
+ .probe = nvt_gmac_probe,
+ .remove = stmmac_pltfr_remove,
+ .driver = {
+ .name = "nuvoton-dwmac",
+ .pm = &stmmac_pltfr_pm_ops,
+ .of_match_table = nvt_dwmac_match,
+ },
+};
+module_platform_driver(nvt_dwmac_driver);
+
+MODULE_AUTHOR("Joey Lu <a0987203069@gmail.com>");
+MODULE_DESCRIPTION("Nuvoton DWMAC specific glue layer");
+MODULE_LICENSE("GPL");
--
2.43.0
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