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charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Russell, kernel test robot noticed the following build warnings: [auto build test WARNING on net-next/main] url: https://github.com/intel-lab-lkp/linux/commits/Russell-King-Oracle/net-stmmac-report-active-PHY-interface/20260126-201908 base: net-next/main patch link: https://lore.kernel.org/r/E1vkLXO-00000005uxQ-31ZV%40rmk-PC.armlinux.org.uk patch subject: [PATCH net-next] net: stmmac: report active PHY interface config: m68k-allyesconfig (https://download.01.org/0day-ci/archive/20260127/202601270336.BzkH3lDa-lkp@intel.com/config) compiler: m68k-linux-gcc (GCC) 15.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260127/202601270336.BzkH3lDa-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202601270336.BzkH3lDa-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c:41:10: warning: 'PHY_INTF_RGMII' redefined 41 | #define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1) | ^~~~~~~~~~~~~~ In file included from drivers/net/ethernet/stmicro/stmmac/stmmac.h:20, from drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h:12, from drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c:17: drivers/net/ethernet/stmicro/stmmac/common.h:328:9: note: this is the location of the previous definition 328 | #define PHY_INTF_RGMII 1 | ^~~~~~~~~~~~~~ vim +/PHY_INTF_RGMII +41 drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c 33a1a01e3afa72 Jisheng Zhang 2024-11-03 18 33a1a01e3afa72 Jisheng Zhang 2024-11-03 19 #define GMAC_CLK_EN 0x00 33a1a01e3afa72 Jisheng Zhang 2024-11-03 20 #define GMAC_TX_CLK_EN BIT(1) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 21 #define GMAC_TX_CLK_N_EN BIT(2) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 22 #define GMAC_TX_CLK_OUT_EN BIT(3) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 23 #define GMAC_RX_CLK_EN BIT(4) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 24 #define GMAC_RX_CLK_N_EN BIT(5) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 25 #define GMAC_EPHY_REF_CLK_EN BIT(6) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 26 #define GMAC_RXCLK_DELAY_CTRL 0x04 33a1a01e3afa72 Jisheng Zhang 2024-11-03 27 #define GMAC_RXCLK_BYPASS BIT(15) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 28 #define GMAC_RXCLK_INVERT BIT(14) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 29 #define GMAC_RXCLK_DELAY GENMASK(4, 0) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 30 #define GMAC_TXCLK_DELAY_CTRL 0x08 33a1a01e3afa72 Jisheng Zhang 2024-11-03 31 #define GMAC_TXCLK_BYPASS BIT(15) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 32 #define GMAC_TXCLK_INVERT BIT(14) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 33 #define GMAC_TXCLK_DELAY GENMASK(4, 0) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 34 #define GMAC_PLLCLK_DIV 0x0c 33a1a01e3afa72 Jisheng Zhang 2024-11-03 35 #define GMAC_PLLCLK_DIV_EN BIT(31) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 36 #define GMAC_PLLCLK_DIV_NUM GENMASK(7, 0) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 37 #define GMAC_GTXCLK_SEL 0x18 33a1a01e3afa72 Jisheng Zhang 2024-11-03 38 #define GMAC_GTXCLK_SEL_PLL BIT(0) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 39 #define GMAC_INTF_CTRL 0x1c 33a1a01e3afa72 Jisheng Zhang 2024-11-03 40 #define PHY_INTF_MASK BIT(0) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 @41 #define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 42 #define PHY_INTF_MII_GMII FIELD_PREP(PHY_INTF_MASK, 0) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 43 #define GMAC_TXCLK_OEN 0x20 33a1a01e3afa72 Jisheng Zhang 2024-11-03 44 #define TXCLK_DIR_MASK BIT(0) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 45 #define TXCLK_DIR_OUTPUT FIELD_PREP(TXCLK_DIR_MASK, 0) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 46 #define TXCLK_DIR_INPUT FIELD_PREP(TXCLK_DIR_MASK, 1) 33a1a01e3afa72 Jisheng Zhang 2024-11-03 47 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki