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From: Jakub Kicinski <kuba@kernel.org>
To: dan.carpenter@linaro.org
Cc: Jakub Kicinski <kuba@kernel.org>,
	jan.petrous@oss.nxp.com, davem@davemloft.net,
	edumazet@google.com, pabeni@redhat.com,
	mcoquelin.stm32@gmail.com, imx@lists.linux.dev,
	chester62515@gmail.com, mbrugger@suse.com,
	netdev@vger.kernel.org, s32@nxp.com, conor+dt@kernel.org,
	andrew+netdev@lunn.ch, robh@kernel.org, kernel@pengutronix.de,
	linux-stm32@st-md-mailman.stormreply.com, shawnguo@kernel.org,
	linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com,
	linaro-s32@linaro.org, linux-arm-kernel@lists.infradead.org,
	alexandre.torgue@foss.st.com, krzk+dt@kernel.org,
	devicetree@vger.kernel.org, festevam@gmail.com,
	s.hauer@pengutronix.de
Subject: Re: [v5,2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon
Date: Wed, 28 Jan 2026 21:10:35 -0800	[thread overview]
Message-ID: <20260129051035.375905-1-kuba@kernel.org> (raw)
In-Reply-To: <939fdaf94038613486bdbba510a92a1e57e18c71.1769592679.git.dan.carpenter@linaro.org>

This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.

For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon

This commit adds the nxp,phy-sel property to the S32 DWMAC binding,
allowing access to the GMAC_0_CTRL_STS register via a syscon interface
instead of the previous ad-hoc direct register mapping.

> diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> index 2b8b74c5feec..65633b10e49e 100644
> --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml

[ ... ]

> +  nxp,phy-sel:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle to the GPR syscon node
> +          - description: offset of PHY selection register
> +    description:
> +      This phandle points to the GMAC_0_CTRL_STS register which controls the
> +      GMAC_0 configuration options.  The register lets you select the PHY
> +      interface and the PHY mode.  It also controls if the FTM_0 or FTM_1
> +      FlexTimer Modules connect to GMAC_O.
                                       ^^^^^^

Should this be GMAC_0 (with a zero) instead of GMAC_O (with a letter O)?
The rest of the description uses GMAC_0_CTRL_STS and GMAC_0 consistently.
-- 
pw-bot: cr

  reply	other threads:[~2026-01-29  5:10 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-28  9:53 [PATCH v5 0/3] s32g: Use a syscon for GPR Dan Carpenter
2026-01-28  9:54 ` [PATCH v5 1/3] net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII Dan Carpenter
2026-01-28 12:30   ` Jan Petrous
2026-01-28  9:54 ` [PATCH v5 2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Dan Carpenter
2026-01-29  5:10   ` Jakub Kicinski [this message]
2026-01-28  9:54 ` [PATCH v5 3/3] dts: s32g: Add GPR syscon region Dan Carpenter

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