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From: Simon Horman <horms@kernel.org>
To: ivecera@redhat.com
Cc: Simon Horman <horms@kernel.org>,
	richardcochran@gmail.com, arkadiusz.kubalewski@intel.com,
	przemyslaw.kitszel@intel.com, aleksandr.loktionov@intel.com,
	andrew+netdev@lunn.ch, pabeni@redhat.com, saeedm@nvidia.com,
	kuba@kernel.org, tariqt@nvidia.com, netdev@vger.kernel.org,
	grzegorz.nitka@intel.com, poros@redhat.com, davem@davemloft.net,
	vadim.fedorenko@linux.dev, linux-rdma@vger.kernel.org,
	linux-kernel@vger.kernel.org, aleksander.lobakin@intel.com,
	jonathan.lemon@gmail.com, jiri@resnulli.us,
	anthony.l.nguyen@intel.com, intel-wired-lan@lists.osuosl.org,
	Prathosh.Satish@microchip.com, leon@kernel.org,
	edumazet@google.com, mbloch@nvidia.com
Subject: Re: [net-next,v4,9/9] ice: dpll: Support E825-C SyncE and dynamic pin discovery
Date: Tue,  3 Feb 2026 16:11:20 +0000	[thread overview]
Message-ID: <20260203161120.1894163-1-horms@kernel.org> (raw)
In-Reply-To: <20260202171638.17427-10-ivecera@redhat.com>

This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.

For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
ice: dpll: Support E825-C SyncE and dynamic pin discovery

This patch implements SyncE support for the E825-C Ethernet controller
using the DPLL subsystem, with dynamic pin discovery via firmware (ACPI)
and asynchronous registration using the DPLL notifier chain.

> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
> index 4eca62688d83..a8c99e49bfae 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dpll.c
> +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c

[ ... ]

> @@ -528,6 +529,92 @@ ice_dpll_pin_disable(struct ice_hw *hw, struct ice_dpll_pin *pin,
>  	return ret;
>  }
>
> +/**
> + * ice_dpll_rclk_update - updates the state of rclk pin on a device
> + * @pf: private board struct
> + * @pin: pointer to a pin
> + * @port_num: port number
> + *
> + * Update struct holding pin states info, states are separate for each parent
> + *
> + * Context: Called under pf->dplls.lock
> + * Return:
> + * * 0 - OK
> + * * negative - error
> + */
> +static int ice_dpll_rclk_update(struct ice_pf *pf, struct ice_dpll_pin *pin,
> +				u8 port_num)
> +{
> +	int ret;
> +
> +	for (u8 parent = 0; parent < pf->dplls.rclk.num_parents; parent++) {
> +		ret = ice_aq_get_phy_rec_clk_out(&pf->hw, &parent, &port_num,
> +						 &pin->flags[parent], NULL);

Is it safe to pass &parent as an output parameter when it's also the loop
counter? Looking at ice_aq_get_phy_rec_clk_out():

    int ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, ...)
    {
        cmd->phy_output = *phy_output;  // Read as input
        status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
        if (!status) {
            *phy_output = cmd->phy_output;  // Write back from firmware
        ...

The firmware could potentially return a different value than was sent,
which would be written back to 'parent', corrupting the loop counter.

This corrupted value is then used as an array index:

> +		if (ret)
> +			return ret;
> +
> +		ice_dpll_pin_store_state(pin, parent,
> +					 ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN &
> +					 pin->flags[parent]);

Both pin->flags[parent] and pin->state[parent] (inside
ice_dpll_pin_store_state) could access out of bounds if firmware returns
a value >= ICE_DPLL_RCLK_NUM_MAX (which is 2).

Would it be safer to use a separate variable for the phy_output parameter
and validate that firmware echoes back the expected value?

> +	}
> +
> +	return 0;
> +}

[ ... ]

> @@ -3239,8 +3683,8 @@ static int ice_dpll_init_pins(struct ice_pf *pf, bool cgu)
>   * @d: pointer to ice_dpll
>   * @cgu: if cgu is present and controlled by this NIC
>   *
> - * If cgu is owned unregister the dpll from dpll subsystem.
> - * Release resources of dpll device from dpll subsystem.
> + * If cgu is owned, unregister the DPL from DPLL subsystem.
> + * Release resources of DPLL device from DPLL subsystem.
>   */

This isn't a bug, but there's a typo: 'DPL' should be 'DPLL'.

  reply	other threads:[~2026-02-03 16:11 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-02 17:16 [PATCH net-next v4 0/9] dpll: Core improvements and ice E825-C SyncE support Ivan Vecera
2026-02-02 17:16 ` [PATCH net-next v4 1/9] dpll: Allow associating dpll pin with a firmware node Ivan Vecera
2026-02-02 17:16 ` [PATCH net-next v4 2/9] dpll: zl3073x: Associate pin with fwnode handle Ivan Vecera
2026-02-02 17:16 ` [PATCH net-next v4 3/9] dpll: Add notifier chain for dpll events Ivan Vecera
2026-02-02 17:16 ` [PATCH net-next v4 4/9] dpll: Support dynamic pin index allocation Ivan Vecera
2026-02-02 17:16 ` [PATCH net-next v4 5/9] dpll: zl3073x: Add support for mux pin type Ivan Vecera
2026-02-02 17:16 ` [PATCH net-next v4 6/9] dpll: Enhance and consolidate reference counting logic Ivan Vecera
2026-02-02 17:16 ` [PATCH net-next v4 7/9] dpll: Add reference count tracking support Ivan Vecera
2026-02-02 21:48   ` [Intel-wired-lan] " kernel test robot
2026-02-03 10:21     ` Ivan Vecera
2026-02-02 23:55   ` kernel test robot
2026-02-03 16:11   ` [net-next,v4,7/9] " Simon Horman
2026-02-03 17:08     ` Ivan Vecera
2026-02-02 17:16 ` [PATCH net-next v4 8/9] drivers: Add support for DPLL reference count tracking Ivan Vecera
2026-02-02 17:16 ` [PATCH net-next v4 9/9] ice: dpll: Support E825-C SyncE and dynamic pin discovery Ivan Vecera
2026-02-03 16:11   ` Simon Horman [this message]
2026-02-03 17:16     ` [net-next,v4,9/9] " Ivan Vecera

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