Re: [PATCH net-next v14 3/4] net: dsa: yt921x: Add support for Motorcomm YT921x

[yangfl <mmyangfl@gmail.com>]

On Wed, Feb 4, 2026 at 3:12 PM michio da neko <michio.haiyaku@gmail.com> wrote:
>
> Hi David Yang,
>
> I am testing your YT9215 driver on a CIG device (ODM for a carrier)
> which uses the Qualcomm IPQ5018 SoC paired with the Motorcomm YT9215S
> switch.
>
> The switch itself is detected correctly via MDIO bitbang, but I am
> facing issues with the internal PHYs. They are detected with a specific
> ID |0x01e04281| which falls back to the "Generic PHY" driver, and the
> ports remain in |NO-CARRIER| state even when cables are plugged in. I
> tried the existing Motorcomm PHY driver but it does not seem to cover
> this specific ID.
>
> Here is my setup details:
>
> DTS Configuration: I am using phy-mode = "internal" for the ports. (Full
> DTS available here:
> https://github.com/michioxd/openwrt-wf810df/blob/1b37e3adee7ab6651430511af259687a5a57edc5/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-ax3000cv2.dts)
>
>
> &mdio_bitbang {
>      /* ... */
>      yt9215: switch@1d {
>          compatible = "motorcomm,yt9215";
>          reg = <29>;
>          /* ... */
>          ethernet-ports {
>              ethernet-port@0 {
>                  reg = <0>;
>                  phy-mode = "internal";
>                  phy-handle = <&sw_phy0>;
>              };
>              /* ... */
>          };
>      };
> };
>
>
> dmesg Output: The chip ID is detected as 0x90020002, but PHYs are generic:
>
>
> [   13.405614] yt921x gpio-1:1d: Motorcomm YT9215S ethernet switch,
> chipid: 0x90020002, chipmode: 0x2 0x0
> [   14.004664] yt921x gpio-1:1d: configuring for fixed/2500base-x link mode
> [   14.018058] yt921x gpio-1:1d: Link is Up - 2.5Gbps/Full - flow
> control off
> [   14.097426] yt921x gpio-1:1d lan1 (uninitialized): PHY [gpio-1:1d:00]
> driver [Generic PHY] (irq=POLL)
> [   14.160182] yt921x gpio-1:1d lan2 (uninitialized): PHY [gpio-1:1d:01]
> driver [Generic PHY] (irq=POLL)
> [   14.226811] yt921x gpio-1:1d lan3 (uninitialized): PHY [gpio-1:1d:02]
> driver [Generic PHY] (irq=POLL)
>
>
> ip link Output:
>
>
> 3: lan: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1508 qdisc fq_codel state
> UP qlen 1000
>      link/ether ... brd ff:ff:ff:ff:ff:ff
> 4: lan1@lan: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
> master br-lan state LOWERLAYERDOWN qlen 1000
>      link/ether ... brd ff:ff:ff:ff:ff:ff
> 5: lan2@lan: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
> master br-lan state LOWERLAYERDOWN qlen 1000
>      link/ether ... brd ff:ff:ff:ff:ff:ff
> 6: lan3@lan: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
> master br-lan state LOWERLAYERDOWN qlen 1000
>      link/ether ... brd ff:ff:ff:ff:ff:ff
>
> Have you encountered this PHY ID (0x01e04281) before? If this ID
> requires a driver patch, do you know if it shares the same register
> layout or behavior with any existing supported YT8xxx PHYs (like YT8511
> or YT8521)? Knowing its closest relative would help me attempt to add
> support for it in drivers/net/phy/motorcomm.c.
>
> Any advice on how to bring up these ports would be appreciated.
>
> Best regards, Michio
>
> --
> michio da neko
> https://michioxd.ch
>

Hi,

Please do not use PATCH thread for technical support, as it CCs to
tons of unrelated people.

If you are looking closer you might find the thread about the chip on
the OpenWRT forum.

As for your question, the internal PHYs are standard and do not need a
separate driver for basic support.