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[96.255.20.138]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cb39da3dc6sm401861185a.51.2026.02.13.08.14.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 08:14:13 -0800 (PST) From: Gregory Price To: Alejandro Lucero Cc: linux-cxl@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 22/22] sfc: support pio mapping based on cxl Date: Fri, 13 Feb 2026 11:14:07 -0500 Message-ID: <20260213161410.2945294-3-gourry@gourry.net> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260201155438.2664640-23-alejandro.lucero-palau@amd.com> References: <20260201155438.2664640-1-alejandro.lucero-palau@amd.com> <20260201155438.2664640-23-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This review was generated by kreview-0811365ff2. =0D =0D This is not an automated email, the reviewer though this report=0D looked valid enough to consider discussion.=0D =0D ----=0D I am completely unfamiliar with this code, but the question it poses=0D at least seems reasonable.=0D =0D ~Gregory=0D ----=0D =0D On Sat, Feb 01, 2026, Alejandro Lucero wrote:=0D =0D > diff --git a/drivers/net/ethernet/sfc/ef10.c b/drivers/net/ethernet/sfc/e= f10.c=0D > index fcec81f862ec..2bb6d3136c7c 100644=0D > --- a/drivers/net/ethernet/sfc/ef10.c=0D > +++ b/drivers/net/ethernet/sfc/ef10.c=0D =0D [ ... ]=0D =0D > @@ -1263,8 +1281,25 @@ static int efx_ef10_dimension_resources(struct efx= _nic *efx)=0D > iounmap(efx->membase);=0D > efx->membase =3D membase;=0D >=0D > - /* Set up the WC mapping if needed */=0D > - if (wc_mem_map_size) {=0D > + if (!wc_mem_map_size)=0D > + goto skip_pio;=0D > +=0D > + /* Set up the WC mapping */=0D > +=0D > +#ifdef CONFIG_SFC_CXL=0D > + probe_data =3D container_of(efx, struct efx_probe_data, efx);=0D > + if ((nic_data->datapath_caps3 &=0D > + (1 << MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_LBN)) &&=0D > + probe_data->cxl_pio_initialised) {=0D > + /* Using PIO through CXL mapping? */=0D > + nic_data->pio_write_base =3D probe_data->cxl->ctpio_cxl +=0D > + (pio_write_vi_base * efx->vi_stride +=0D > + ER_DZ_TX_PIOBUF - uc_mem_map_size);=0D > + probe_data->cxl_pio_in_use =3D true;=0D > + } else=0D > +#endif=0D > + {=0D > + /* Using legacy PIO BAR mapping */=0D > nic_data->wc_membase =3D ioremap_wc(efx->membase_phys +=0D > uc_mem_map_size,=0D > wc_mem_map_size);=0D > @@ -1279,12 +1314,13 @@ static int efx_ef10_dimension_resources(struct ef= x_nic *efx)=0D > nic_data->wc_membase +=0D > (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -=0D > uc_mem_map_size);=0D > -=0D > - rc =3D efx_ef10_link_piobufs(efx);=0D > - if (rc)=0D > - efx_ef10_free_piobufs(efx);=0D > }=0D =0D The CXL path sets nic_data->pio_write_base but does not set=0D nic_data->pio_write_vi_base, while the legacy path does:=0D =0D nic_data->pio_write_vi_base =3D pio_write_vi_base;=0D =0D Since nic_data is kzalloc'd, pio_write_vi_base stays at 0 in the CXL=0D path. efx_ef10_link_piobufs() then uses nic_data->pio_write_vi_base=0D to issue MC_CMD_LINK_PIOBUF commands:=0D =0D MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,=0D nic_data->pio_write_vi_base + index);=0D =0D and also for the special-case check:=0D =0D if (tx_queue->queue =3D=3D nic_data->pio_write_vi_base) {=0D =0D Wouldn't this link PIO buffers to incorrect VI instances when using=0D CXL, since the local variable pio_write_vi_base has the correct=0D non-zero value but the struct field was never updated?=0D