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Tue, 17 Feb 2026 23:29:29 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Jacob Keller , Jianbo Liu Subject: [PATCH net V2 3/6] net/mlx5: Fix misidentification of write combining CQE during poll loop Date: Wed, 18 Feb 2026 09:29:01 +0200 Message-ID: <20260218072904.1764634-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260218072904.1764634-1-tariqt@nvidia.com> References: <20260218072904.1764634-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013B:EE_|BN7PPFFC4F04B28:EE_ X-MS-Office365-Filtering-Correlation-Id: 805a9d70-1980-4d42-b2ad-08de6ebf7fe7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?WnZrod0Z/Eot+U8B/sLcEmca+p/ShEnPCgxMprD/fBz4t0/bcUpJpzCeSf8k?= =?us-ascii?Q?40HoT6267+T3xNJ7/uZWI4Tg4994XLY+SvSOzYrQiC3yFuI2Lo/vA/8Qw0wU?= =?us-ascii?Q?Vl0EW+qvvy9cB4XicHTwza37tHzjBbeACheSrQ6UvDn6hPIRU+Lup7/jsDKH?= =?us-ascii?Q?DtEo3qjhgrX1c8Voiv4OHCndI+mwLj8J8p5+0V9BVgqKWzyUwPXyUdNB06Jg?= =?us-ascii?Q?oLzu6IXLKFMbmza3bpi0vzZCUfz0QZRRHBTjTszPajc11RSHs/xRTR0kQKc8?= =?us-ascii?Q?2+pG3HxZeOJfENBJ9KI74VWa8oZHK/RWNODQEtKPyZ4qZyUVK6pdBx8fSW84?= =?us-ascii?Q?XrdUu39JRaFBz6iomK4sub34ERPFQ8gSza5BTc5glgOyWG4tbcPJQJ81EaH9?= =?us-ascii?Q?Ym1RXYDjC081ZpnsG52PLgGtbWKgYfg0onE4hqsWlKjFD5pdsU+pWK8+xNFA?= =?us-ascii?Q?bA026mp87NoombheCXyoQnxmIRWycOR8ogQtzc4D2GgojcxyDErJDsPpdBQo?= =?us-ascii?Q?0CdvbpOpsTquyvM6y6IwR8m9BPreiE/NBvV+sO+ntxpg6N8m7912EVVbjgFx?= =?us-ascii?Q?dQalqb70AApJ8SS58KrpZv5YnhhN3tA6BJUoLnKGxId6XMX3XR95gCfVNcjM?= =?us-ascii?Q?m2k3vznvc06fAIcMy/N4UkW5XaRcKD7i8te3ALQdsj5BXOVkS2+DcPTVRDwV?= =?us-ascii?Q?zGuScuEVL/LBe+Ro9esbFqEB/6rkGUzIZQIY/muLLHtcRUPfNXo24fcTjHgC?= =?us-ascii?Q?zje6h+qSoqv1xxyI/2wW68bepYwoa7xTRMW6s9bF/x3Cay8vV7kx+JVtW8mD?= =?us-ascii?Q?OdVNDp75sVRX5HpqLkQg45CeYpijp7OCvV6Bek+rbonbWuQJ15X5v9aea0oG?= =?us-ascii?Q?AJ7TQPAKVu/c5noELMan8tKdzDn7ZayT/KEHH2jG6NRrHsRlf+8c6l0Qlu8p?= =?us-ascii?Q?AmI4wLoEL95HBQGGjAD6dQm+VBS6fikph/554vMqW+AbvETm9e8XKeyvgZDU?= =?us-ascii?Q?A/r0R/b2b+r3XfLC6sgHYfDOteoEO6WT4dT/1OOcuY9jJ5O5OE9vLii7Hcsw?= =?us-ascii?Q?vz4lyJYtnjZDTG0FY31p3L/tc6q+vW2zSsInENu1ytybwx9aNA8iRZAny2ir?= =?us-ascii?Q?rMrT8cahjd/ud6ctAcFYLZZ+cHl25rQ3c5cn5rHezleAaLJhZ9V//0Sz19C2?= =?us-ascii?Q?pWUwafYARetG15mZyw+M02cNqK8zUnEFnW+jmD8JuJ5V5eR7xgwfBOkTzrZ0?= =?us-ascii?Q?+ATQA7+JKWR20PkV/DJlJWoUv+oQwVATCHxAiaiAaFs8Zcr2MfO0AaLN2mz9?= =?us-ascii?Q?GrZFfr4zW4MgpzDcBuXb7fhzpwTDvUE72joRjBj5SYeYjkt65sHVL1tFMEaD?= =?us-ascii?Q?lIioMohbQsts69mJ872Ss4XkqcN+GuIU2FEZda/hL8xaz4kWO/x036hE5lvW?= =?us-ascii?Q?k9C2Qp1PwSoX/9bhD9MpNkk1VhyH/rgb3sNv+nAjPTGctqQwWHBQp7HndSZC?= =?us-ascii?Q?41+BmPfe7vKCkgNUcKbZZbbbBEzyXw/ruAY5Fg5BLpN3oqJcS/uNNiMOtvfK?= =?us-ascii?Q?2Xvcuj2LgfWOgndiI3BjbPIcj/d5T0cFUud18o09w8Qvvxy31w/jmwELxCv8?= =?us-ascii?Q?sTX7N1lF2OV3l8vNv2a87R0U/heQQ3jj9A6fkRdWw6n7/Xch1uG48Oo+fXv+?= =?us-ascii?Q?8yn4xg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(7416014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +0lfiZguQPrWEul7GfaIghaehKQ8NVDwGrdnHfZjk/oF036FUXfFl5r6/dGa2BJKKtZbXFESu3jGATogg+T+cBFzAbnTWMY6NO5DTjyAnk9GSJgTsUJqTjGV+ZMYG9DzoGE5qJ9h0yRZ+FVRoWq/tbN8j3FNDtXJrKG9L5yYmY4vUmw16hUQ8y/jlduI9Z0yCGKkWeHdGqzBnI+feZl0H7bVte1XYbQJ+7OQaNm9boPzSSGN6ZQae2m/rhze/LVHXULQMW01CXdNokfZIFx0ShQGi5GuChVKdEFX/eniyIUAZmiy4mAqsjTLXN73ORa6cbUCKs9IUqrZAqFcNSeM7On6LFyMv1jp9R/W6ELNTKuiTNQe0XzCpWSDkoMFT90gA3zg+eKpdZ2O/KZ4RC/kIT9cr9Eicf7UNJC038YpZnNhG4jqJZoRPG54UbWgfy40 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2026 07:29:49.5328 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 805a9d70-1980-4d42-b2ad-08de6ebf7fe7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPFFC4F04B28 From: Gal Pressman The write combining completion poll loop uses usleep_range() which can sleep much longer than requested due to scheduler latency. Under load, we witnessed a 20ms+ delay until the process was rescheduled, causing the jiffies based timeout to expire while the thread is sleeping. The original do-while loop structure (poll, sleep, check timeout) would exit without a final poll when waking after timeout, missing a CQE that arrived during sleep. Instead of the open-coded while loop, use the kernel's poll_timeout_us() which always performs an additional check after the sleep expiration, and is less error-prone. Note: poll_timeout_us() doesn't accept a sleep range, by passing 10 sleep_us the sleep range effectively changes from 2-10 to 3-10 usecs. Fixes: d98995b4bf98 ("net/mlx5: Reimplement write combining test") Signed-off-by: Gal Pressman Reviewed-by: Jianbo Liu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/wc.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/wc.c b/drivers/net/ethernet/mellanox/mlx5/core/wc.c index 815a7c97d6b0..04d03be1bb77 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/wc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/wc.c @@ -2,6 +2,7 @@ // Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. #include +#include #include #include "lib/clock.h" #include "mlx5_core.h" @@ -15,7 +16,7 @@ #define TEST_WC_NUM_WQES 255 #define TEST_WC_LOG_CQ_SZ (order_base_2(TEST_WC_NUM_WQES)) #define TEST_WC_SQ_LOG_WQ_SZ TEST_WC_LOG_CQ_SZ -#define TEST_WC_POLLING_MAX_TIME_JIFFIES msecs_to_jiffies(100) +#define TEST_WC_POLLING_MAX_TIME_USEC (100 * USEC_PER_MSEC) struct mlx5_wc_cq { /* data path - accessed per cqe */ @@ -359,7 +360,6 @@ static int mlx5_wc_poll_cq(struct mlx5_wc_sq *sq) static void mlx5_core_test_wc(struct mlx5_core_dev *mdev) { unsigned int offset = 0; - unsigned long expires; struct mlx5_wc_sq *sq; int i, err; @@ -389,13 +389,9 @@ static void mlx5_core_test_wc(struct mlx5_core_dev *mdev) mlx5_wc_post_nop(sq, &offset, true); - expires = jiffies + TEST_WC_POLLING_MAX_TIME_JIFFIES; - do { - err = mlx5_wc_poll_cq(sq); - if (err) - usleep_range(2, 10); - } while (mdev->wc_state == MLX5_WC_STATE_UNINITIALIZED && - time_is_after_jiffies(expires)); + poll_timeout_us(mlx5_wc_poll_cq(sq), + mdev->wc_state != MLX5_WC_STATE_UNINITIALIZED, 10, + TEST_WC_POLLING_MAX_TIME_USEC, false); mlx5_wc_destroy_sq(sq); -- 2.44.0