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From: Simon Horman <horms@kernel.org>
To: anthony.l.nguyen@intel.com
Cc: Simon Horman <horms@kernel.org>,
	joshua.a.hay@intel.com, aaron.ma@canonical.com,
	przemyslaw.kitszel@intel.com, Samuel.salin@intel.com,
	jacob.e.keller@intel.com, pmenzel@molgen.mpg.de,
	sridhar.samudrala@intel.com, brett.creeley@amd.com,
	decot@google.com, david.m.ertman@intel.com,
	andrew+netdev@lunn.ch, netdev@vger.kernel.org,
	intel-wired-lan@lists.osuosl.org, sreedevi.joshi@intel.com,
	rafal.romanowski@intel.com, en-wei.wu@canonical.com,
	dima.ruinskiy@intel.com, michal.kubiak@intel.com,
	tglx@kernel.org, pabeni@redhat.com, willemb@google.com,
	avigailx.dahan@intel.com, davem@davemloft.net,
	aleksandr.loktionov@intel.com, edumazet@google.com,
	piotr.kwapulinski@intel.com, sx.rinitha@intel.com,
	emil.s.tantilov@intel.com, brianvv@google.com,
	vitaly.lifshits@intel.com, jedrzej.jagielski@intel.com,
	stable@vger.kernel.org, kuba@kernel.org,
	richardcochran@gmail.com, joe@dama.to, mschmidt@redhat.com,
	boolli@google.com
Subject: Re: [net,13/13] e1000e: correct TIMINCA on ADP/TGP systems with wrong XTAL frequency
Date: Sun, 22 Feb 2026 16:28:35 +0000	[thread overview]
Message-ID: <20260222162835.23954-1-horms@kernel.org> (raw)
In-Reply-To: <20260220004027.729384-14-anthony.l.nguyen@intel.com>

This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.

For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
e1000e: correct TIMINCA on ADP/TGP systems with wrong XTAL frequency

On some Tiger Lake (TGP) and Alder Lake (ADP) platforms, the hardware
XTAL clock is incorrectly interpreted as 24 MHz instead of the actual
38.4 MHz. The commit measures PHC vs system time over 1 ms and if the
delta exceeds 100 microseconds, reprograms TIMINCA for the 38.4 MHz
profile and reinitializes the timecounter.

> diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
> index 814698807f3d..ae35ac479026 100644
> --- a/drivers/net/ethernet/intel/e1000e/netdev.c
> +++ b/drivers/net/ethernet/intel/e1000e/netdev.c

[ ... ]

> @@ -3905,6 +3905,80 @@ static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
>  		e1000_flush_rx_ring(adapter);
>  }
>
> +/**
> + * e1000e_xtal_tgp_workaround - Adjust XTAL clock based on PHC and system
> + * clock delta.
> + * @adapter: Pointer to the private adapter structure
> + *
> + * Measures the time difference between the PHC (Precision Hardware Clock)
> + * and the system clock over a 1 millisecond interval. If the delta
> + * exceeds 100 microseconds, reconfigure the XTAL clock to 38.4 MHz.
> + */
> +static void e1000e_xtal_tgp_workaround(struct e1000_adapter *adapter)
> +{
> +	s64 phc_delta, sys_delta, sys_start_ns, sys_end_ns, delta_ns;
> +	struct ptp_system_timestamp sys_start = {}, sys_end = {};
> +	struct ptp_clock_info *info = &adapter->ptp_clock_info;
> +	struct timespec64 phc_start, phc_end;
> +	struct e1000_hw *hw = &adapter->hw;
> +	struct netlink_ext_ack extack = {};
> +	unsigned long flags;
> +	u32 timinca;
> +	s32 ret_val;
> +
> +	/* Capture start */
> +	if (info->gettimex64(info, &phc_start, &sys_start)) {
> +		e_dbg("PHC gettimex(start) failed\n");
> +		return;
> +	}
> +
> +	/* Small interval to measure increment */
> +	usleep_range(1000, 1100);
> +
> +	/* Capture end */
> +	if (info->gettimex64(info, &phc_end, &sys_end)) {
> +		e_dbg("PHC gettimex(end) failed\n");
> +		return;
> +	}
> +
> +	/* Compute deltas */
> +	phc_delta = timespec64_to_ns(&phc_end) -
> +		    timespec64_to_ns(&phc_start);
> +
> +	sys_start_ns = (timespec64_to_ns(&sys_start.pre_ts) +
> +			timespec64_to_ns(&sys_start.post_ts)) >> 1;
> +
> +	sys_end_ns = (timespec64_to_ns(&sys_end.pre_ts) +
> +		      timespec64_to_ns(&sys_end.post_ts)) >> 1;
> +
> +	sys_delta = sys_end_ns - sys_start_ns;
> +
> +	delta_ns = phc_delta - sys_delta;
> +	if (delta_ns > 100000) {
> +		e_dbg("Corrected PHC frequency: TIMINCA set for 38.4 MHz\n");
> +		/* Program TIMINCA for 38.4 MHz */
> +		timinca = (INCPERIOD_38400KHZ <<
> +			   E1000_TIMINCA_INCPERIOD_SHIFT) |
> +			  (((INCVALUE_38400KHZ <<
> +			     adapter->cc.shift) &
> +			   E1000_TIMINCA_INCVALUE_MASK));

Is adapter->cc.shift correct here? When e1000e_xtal_tgp_workaround runs,
the earlier call to e1000e_get_base_timinca (via e1000e_phc_adjfine in
e1000e_systim_reset) has already set adapter->cc.shift based on the
incorrectly reported 24 MHz XTAL frequency.

On affected hardware where SYSCFI reports 24 MHz:

e1000e_systim_reset()
 -> e1000e_phc_adjfine(0)
    -> e1000e_get_base_timinca() sets:
       adapter->cc.shift = INCVALUE_SHIFT_24MHZ (14)
 -> e1000e_xtal_tgp_workaround()

So when computing TIMINCA for 38.4 MHz, the code uses shift=14:

  INCVALUE_38400KHZ << 14 = 26 << 14 = 425984

But the 38.4 MHz profile needs shift=19:

  INCVALUE_38400KHZ << 19 = 26 << 19 = 13631488

This produces timinca = 17203200 instead of the correct 30408704.

Additionally, the subsequent timecounter_init call uses adapter->cc which
still has shift=14. This computes tc->mask = (1ULL << 14) - 1 = 16383
instead of the correct (1ULL << 19) - 1 = 524287.

Should the function update adapter->cc.shift = INCVALUE_SHIFT_38400KHZ
before computing timinca and calling timecounter_init, matching the
pattern in e1000e_get_base_timinca for the 38.4 MHz profile?

> +		ew32(TIMINCA, timinca);
> +
> +		/* reset the systim ns time counter */
> +		spin_lock_irqsave(&adapter->systim_lock, flags);
> +		timecounter_init(&adapter->tc, &adapter->cc,
> +				 ktime_to_ns(ktime_get_real()));
> +		spin_unlock_irqrestore(&adapter->systim_lock, flags);
> +
> +		/* restore the previous hwtstamp configuration settings */
> +		ret_val = e1000e_config_hwtstamp(adapter,
> +						 &adapter->hwtstamp_config,
> +						 &extack);
> +		if (ret_val && extack._msg)
> +			e_err("%s\n", extack._msg);
> +	}
> +}

[ ... ]

  reply	other threads:[~2026-02-22 16:30 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-20  0:40 [PATCH net 00/13][pull request] Intel Wired LAN Driver Updates 2026-02-19 (idpf, ice, i40e, ixgbevf, e1000e) Tony Nguyen
2026-02-20  0:40 ` [PATCH net 01/13] idpf: increment completion queue next_to_clean in sw marker wait routine Tony Nguyen
2026-02-20  0:40 ` [PATCH net 02/13] idpf: skip deallocating bufq_sets from rx_qgrp if it is NULL Tony Nguyen
2026-02-20  0:40 ` [PATCH net 03/13] idpf: skip deallocating txq group's txqs " Tony Nguyen
2026-02-20  0:40 ` [PATCH net 04/13] idpf: nullify pointers after they are freed Tony Nguyen
2026-02-20  0:40 ` [PATCH net 05/13] idpf: change IRQ naming to match netdev and ethtool queue numbering Tony Nguyen
2026-02-20  0:40 ` [PATCH net 06/13] idpf: Fix flow rule delete failure due to invalid validation Tony Nguyen
2026-02-20  0:40 ` [PATCH net 07/13] ice: recap the VSI and QoS info after rebuild Tony Nguyen
2026-02-20  0:40 ` [PATCH net 08/13] ice: fix crash in ethtool offline loopback test Tony Nguyen
2026-02-20  0:40 ` [PATCH net 09/13] i40e: Fix preempt count leak in napi poll tracepoint Tony Nguyen
2026-02-20  0:40 ` [PATCH net 10/13] ixgbevf: fix link setup issue Tony Nguyen
2026-02-20  0:40 ` [PATCH net 11/13] e1000e: introduce new board type for Panther Lake PCH Tony Nguyen
2026-02-20  0:40 ` [PATCH net 12/13] e1000e: clear DPG_EN after reset to avoid autonomous power-gating Tony Nguyen
2026-02-20  0:40 ` [PATCH net 13/13] e1000e: correct TIMINCA on ADP/TGP systems with wrong XTAL frequency Tony Nguyen
2026-02-22 16:28   ` Simon Horman [this message]
2026-02-24 22:59     ` [net,13/13] " Tony Nguyen
2026-02-25  0:11       ` Jakub Kicinski
2026-02-25 18:42         ` Tony Nguyen

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