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Mon, 23 Feb 2026 12:42:51 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 03/15] net/mlx5e: Extract max_xsk_wqebbs into its own function Date: Mon, 23 Feb 2026 22:41:43 +0200 Message-ID: <20260223204155.1783580-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC9:EE_|LV9PR12MB9805:EE_ X-MS-Office365-Filtering-Correlation-Id: 29593076-ac45-40d3-e197-08de731c2977 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Yr1bM2JKXHYooYVIxqpBGg2DYbMrUFrMHmXmnzPajnDfTPufDhgrwiPBT2Ye?= =?us-ascii?Q?O48G65iJy4tYN8hXu7iPaj2WUDvepsbZYEP9xFO+uDxXxDPof/kw1Bs7gTVb?= =?us-ascii?Q?h6n8r5wF4FRenZc2SINkM6mcG2J9rlK8ex1gNj3j1VPl5WhGlrxIJgpPzfFa?= =?us-ascii?Q?0lmUgFy0hjL+nBgTCft6mYxkMwdBeRFp1kke1yNzN/04Nf14UA+Y1qmYiyhp?= =?us-ascii?Q?vs0QUJET4m3EIfdfKpuJN3E+aYKTvIBlFWl2zdcgCMR5wHyjfQZV6Shpw0RD?= =?us-ascii?Q?FLsg/e4r18XvHhMOJqZcSnJDvyfD5YeEvCn0ln/qYojuuaBvIxe0V2q4m2o5?= =?us-ascii?Q?D1In5FZobk05nBN1kWncfOnvPGLXyXo8+9Qlg3EGIdYNMMr1LxMJQnrvhhXe?= =?us-ascii?Q?NIJ1bZy0eXZXgMpM43RGDDYCf0rwqkzilsFP4CjLt3QGR07IKZ+vSF9fbOEN?= =?us-ascii?Q?tsMFCbyoKu/fyV0dJT3IPcbZhwelD/oEceHBSgJrhQTF5cjYG9ULxNh6zpTl?= =?us-ascii?Q?Kiz8L2jUBEhsFKm+lQuNqS1c1U1dSM5fRmFBE04gcQj2aJSfdP6wrvhBw5Qo?= =?us-ascii?Q?qVe+SOgoEZI1LWyQRqs30omJWPcjSRZWm9kET6uWQscpmF5qkJMqRxkz8Xl4?= =?us-ascii?Q?OJGiAhsOwhxPMh1d/kBzw/ug6N9wUj05IWRlesw8DI6WGdY6MPOh7y5bZh5Z?= =?us-ascii?Q?/ucJwfSz/STJsN7H6bVq5OldUBwEOVGC+SLYyNOQlQOUkG8GqK/MtCBL0nzt?= =?us-ascii?Q?DVhOB3r3LVTu51WROKQohPtAmzZD/wrby07j90/IEehlWAbDqR3DiK1SN8Hw?= =?us-ascii?Q?G0Oz4I33A6EZT0g3Get8YpZjBozjW3EigwWrEMzRXNcW+1yeglilRGxGwdAN?= =?us-ascii?Q?1asOqipnyMApVl+ZU/uyIaHmswKoeQLF1difL/dRboVTxQ4TYDr3cIRgFCwy?= =?us-ascii?Q?HALrlb6OR513wT2P0cG1LJc3TdaRgdQ4QssZETJawZACfKmLZ3engKoW2McA?= =?us-ascii?Q?AFpbIhnSQ+t04gP7ikQu2Uf72XenEAbAcIi69McYPjoZMcNIktRJ0Ry5VAdo?= =?us-ascii?Q?3hCWM1Lxu0qcVvYN6+IQArwMcunY9nEheyZ7lJoq8b7AgphMq6F96abdU2ot?= =?us-ascii?Q?7yeIoFYELX6loCuU76wnCBJJlBPGo/CMFbIHf3g8lvO9Xfoc1zr/4+dWc7OE?= =?us-ascii?Q?fii82sRsP7vtaAyrcaGy+zUWkkKTziApHB/0LKLPJDCbLTsrt198x4qMEy4k?= =?us-ascii?Q?KXCCMwTZVB8JmFBfYdK+wH/DbFrHvCtZLR1FGR1Ou4hHq9ui+1UEE11kgabM?= =?us-ascii?Q?vEU3PcDoMqUMMyzeVonk4X3u6J5NRDYPP1geO9tVXvBxg6+cEznRxA47l/fb?= =?us-ascii?Q?IQy4TIK4dxIZnjrj+P0QhyRVAfKlXFotUC2H0B8EzexvlyMFXrBTCzSBBtrd?= =?us-ascii?Q?rq3GP4FE+HtG9QtiytEuoWHAuU3DCGca6JCBVP7M/ioCcagBsI9nfixaYkFj?= =?us-ascii?Q?GHEHUdUlZIBYZzH0/sLdknH0/wqf0vsv9JoDsThrhTazZFVbRLn8LvBZK5BM?= =?us-ascii?Q?9UH/oZZ1Os8FIec/rP95t3RjqohqXlxq2wcHKxA1uTEO6Q6pt7i32DuiUMBp?= =?us-ascii?Q?6DKtj/uLl0UaAltlg5fHticIkTS5bVGZpMOjchUZHoc0BYgm/wF4LUG0c/iD?= =?us-ascii?Q?kM618w=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: CJlBvzHTuJi0UlHm0TWeRjyI8sB1jTDUJlFJQ9MehICrpi2GLqm/8+b2ZGFgbCiMpB5aBUY9wDRYFJv4PL8VhUYJDe0dRTxESMBouEDi4SzYU0zsolcMeioXDdlYKYOp/zidogWWSItFZEMTBwp62pBm2Pn/jM+dn9U4JrbjU5YqOc/XEZeswT/rmYPw9dHNJwZGX66HFbq5ylxwWEUqCCZRImiD+1nGzQRDvBLH3haOjZ5PbrKEErqeDqqOT9se2xK23v9PfY91ud/Pa2Yn3aOjd64SWMFGhrMtntYaD9/jGa5gV9IpN+ug56faO9uslZPYVJFY+PlS3Y3f5JFc7aeGAyTr3rTeVuj3oM4bosb7W4l1W0tAbi/hiIGw/Wm+Hlq63SAwL5YjTHa9j5FI2MJe/x+4FisInYfD/aWBaqNADiZrh7jqNvRQd0BXuN+e X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:43:12.3888 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29593076-ac45-40d3-e197-08de731c2977 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV9PR12MB9805 From: Dragos Tatulea Calculating max_xsk_wqebbs seems large enough to deserve its own function. It will make upcoming changes easier. This patch has no functional changes. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en/params.c | 94 ++++++++++--------- 1 file changed, 52 insertions(+), 42 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c index 07d75a85ee7f..be1aa37531de 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -1116,18 +1116,15 @@ static u32 mlx5e_mpwrq_total_umr_wqebbs(struct mlx5_core_dev *mdev, return umr_wqebbs * (1 << mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); } -static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_core_dev *mdev, - struct mlx5e_params *params, - struct mlx5e_rq_param *rq_param) +static u32 mlx5e_max_xsk_wqebbs(struct mlx5_core_dev *mdev, + struct mlx5e_params *params) { - u32 wqebbs, total_pages, useful_space; - - /* MLX5_WQ_TYPE_CYCLIC */ - if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) - return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; + struct mlx5e_xsk_param xsk = {0}; + u32 max_xsk_wqebbs = 0; + u8 frame_shift; - /* UMR WQEs for the regular RQ. */ - wqebbs = mlx5e_mpwrq_total_umr_wqebbs(mdev, params, NULL); + if (!params->xdp_prog) + return 0; /* If XDP program is attached, XSK may be turned on at any time without * restarting the channel. ICOSQ must be big enough to fit UMR WQEs of @@ -1139,41 +1136,54 @@ static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_core_dev *mdev, * from capabilities. Hence, we have to try all valid values of XSK * frame size (and page_shift) to find the maximum. */ - if (params->xdp_prog) { - u32 max_xsk_wqebbs = 0; - u8 frame_shift; - - for (frame_shift = XDP_UMEM_MIN_CHUNK_SHIFT; - frame_shift <= PAGE_SHIFT; frame_shift++) { - /* The headroom doesn't affect the calculation. */ - struct mlx5e_xsk_param xsk = { - .chunk_size = 1 << frame_shift, - .unaligned = false, - }; - - /* XSK aligned mode. */ - max_xsk_wqebbs = max(max_xsk_wqebbs, - mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); - - /* XSK unaligned mode, frame size is a power of two. */ - xsk.unaligned = true; - max_xsk_wqebbs = max(max_xsk_wqebbs, - mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); - - /* XSK unaligned mode, frame size is not equal to stride size. */ - xsk.chunk_size -= 1; - max_xsk_wqebbs = max(max_xsk_wqebbs, - mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); - - /* XSK unaligned mode, frame size is a triple power of two. */ - xsk.chunk_size = (1 << frame_shift) / 4 * 3; - max_xsk_wqebbs = max(max_xsk_wqebbs, - mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); - } + for (frame_shift = XDP_UMEM_MIN_CHUNK_SHIFT; + frame_shift <= PAGE_SHIFT; frame_shift++) { + u32 total_wqebbs; - wqebbs += max_xsk_wqebbs; + /* The headroom doesn't affect the calculations below. */ + + /* XSK aligned mode. */ + xsk.chunk_size = 1 << frame_shift; + xsk.unaligned = false; + total_wqebbs = mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk); + max_xsk_wqebbs = max(max_xsk_wqebbs, total_wqebbs); + + /* XSK unaligned mode, frame size is a power of two. */ + xsk.unaligned = true; + total_wqebbs = mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk); + max_xsk_wqebbs = max(max_xsk_wqebbs, total_wqebbs); + + /* XSK unaligned mode, frame size is not equal to stride + * size. + */ + xsk.chunk_size -= 1; + total_wqebbs = mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk); + max_xsk_wqebbs = max(max_xsk_wqebbs, total_wqebbs); + + /* XSK unaligned mode, frame size is a triple power of two. */ + xsk.chunk_size = (1 << frame_shift) / 4 * 3; + total_wqebbs = mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk); + max_xsk_wqebbs = max(max_xsk_wqebbs, total_wqebbs); } + return max_xsk_wqebbs; +} + +static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_core_dev *mdev, + struct mlx5e_params *params, + struct mlx5e_rq_param *rq_param) +{ + u32 wqebbs, total_pages, useful_space; + + /* MLX5_WQ_TYPE_CYCLIC */ + if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) + return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; + + /* UMR WQEs for the regular RQ. */ + wqebbs = mlx5e_mpwrq_total_umr_wqebbs(mdev, params, NULL); + + wqebbs += mlx5e_max_xsk_wqebbs(mdev, params); + /* UMR WQEs don't cross the page boundary, they are padded with NOPs. * This padding is always smaller than the max WQE size. That gives us * at least (PAGE_SIZE - (max WQE size - MLX5_SEND_WQE_BB)) useful bytes -- 2.44.0