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Mon, 23 Feb 2026 12:43:23 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Richard Cochran , , , , , Gal Pressman , Dragos Tatulea , Cosmin Ratiu , Pavel Begunkov , David Wei Subject: [PATCH net-next 08/15] net/mlx5e: SHAMPO, Always calculate page size Date: Mon, 23 Feb 2026 22:41:48 +0200 Message-ID: <20260223204155.1783580-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260223204155.1783580-1-tariqt@nvidia.com> References: <20260223204155.1783580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000208:EE_|CY3PR12MB9703:EE_ X-MS-Office365-Filtering-Correlation-Id: 117ed158-063d-488b-24ca-08de731c39ad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?7JFra4iSUdAO8zgx7kA+23XbcH55zV3k2ppFBahibsKFo6jDmYOeDXccgkVR?= =?us-ascii?Q?iHdxUBpqE4u91+7MmFeEMUtWw1WRrFZ4kLRpxa+N/z+AExN+iHRdiVM7VKFo?= =?us-ascii?Q?UQ1AVLwtfbpC1hwD0d6whh4A7QIfly1Dga+289sh0epId/0bndN51Xrrzjea?= =?us-ascii?Q?4iAHpNSsGrWsfNPFV8cBP+x2nsysy87d+4C85yVmVKP5IHI8avQYIgVIX52w?= =?us-ascii?Q?NtiF56T2Q50c0HhtSKRKORNt0wwefznkmWQkGUCT9dwp8QVXpLvZKqfIoirc?= =?us-ascii?Q?kK543nFeDHirKNQ9tk3qvBRkE59TIm1XpYiVE3QJlHJKGrIEoNANVdCJIRqw?= =?us-ascii?Q?y61a9sF0yzJgEOTuVLOCHV1kCo5sO+K0T5zfxuUC3JknlDnhPNtwbRKON4It?= =?us-ascii?Q?fBYJcxS9GcSzJJ8pYEv77Bjuuz6N/STDEEJ27dIcdY2gEv8ccf0iNcK35sG1?= =?us-ascii?Q?4Q5+41eKN9bC/KEj3aZeCkTNWuT9kxtal82/0N+cg1gEGP5UTbdecaO7DAnc?= =?us-ascii?Q?QYHGkXujGVXkOp8pWKDOfl5Om7xAIlLHQZGo6gcHciNUmIlPDCjc3bJ0SHHi?= =?us-ascii?Q?ycUzcEis45NBPX0EABL+Na70Oth3eKUTXF97b0+LKXMDcQAs4i9ASlUdB5u5?= =?us-ascii?Q?3XQ4Pzv5W5Zr2Jjj8zQxbItRqNIjaCcUe2F+06E7ldhoJmdheL08cU/AVIgA?= =?us-ascii?Q?aNTGUvn9W7MxEmQ9NL/6PNYA+Ea2yh2hm7rsYGaoWAb33dW9mf2mppPJmIUV?= =?us-ascii?Q?UheDUaP2qhKwxC+S6nY2iv3YJItBX4jkdCAhtesQRd7dQRMgrjSEOdgw3Ji7?= =?us-ascii?Q?eq0CIHFe6gkmTjj4W9mKPzJPsNFmznwvOtfXGIA77dR/ymH2JZC3dhXhwsO7?= =?us-ascii?Q?OwxH7mQdXMDX7CNodU1HrMKg7V3qkYYOH2l/GffTagnuX1Sk501EvDEqHQoP?= =?us-ascii?Q?mi9Y8AthDXDqT2m5wMJF9aH44GvALYLWaPI3r9wuIWn7s4joJpm2F+0vNcNi?= =?us-ascii?Q?a467ebN9+mU7+oXFKv/ewNGTfHAO/Km9VgqMTY2pdgH3NaZ20c/HOmV2HSqP?= =?us-ascii?Q?M5FHJw6te7PN+xo6FNkN6H9w4RxaDvL0dV4say+KUFaHCRxEMkTK+aSFnXHT?= =?us-ascii?Q?P/waC07Q3p9maVuXIFJX+VTZb5IpN610dOvRxWAY8a93/qslFxV9/4jbvBNC?= =?us-ascii?Q?lQKFIvS++OHo53pXZYtYdg/Bnlqh5VxvAkpA24fhwlYR2uc4fLplsqfE0C//?= =?us-ascii?Q?vN09rupVoo7bynz6MlsaAoCAl2F4bpmcu1OGB2Wa8oMExRxK3pc4e4ur8rBF?= =?us-ascii?Q?l9Dyx67cYQ0Rdmtf/RnNKwhIPrtBV/N/z99+RH/nIlCp2Vw5Wx+FTRUrTWCa?= =?us-ascii?Q?KfWobaYlwfBFuBNma15CdxromMfVOkE6aUtGTFLKJT17BvwUI+nmvWzDbILH?= =?us-ascii?Q?MsnCiB1aTzIvUsxAa+3whGjBHcGIz/XGYNHeU6IEWVDhvtJs8Gn/Wd9jE/lf?= =?us-ascii?Q?q8ynyWL30g17WYwkXWRNgL7Inz+zf6THMdq6XNf7UQ2ulzUdQCbuZD/9CrHF?= =?us-ascii?Q?roxcusYvXdU0itY7UJefeq8ldvb6J04JLQ7zJ/xpChXEdwGFsgP4eWgIQkyZ?= =?us-ascii?Q?TuswyiNFqvN5OsHsI9ESV9gHWga7/LdKaQHCOeJXGnqgsVZsTz3h2RoVdaYg?= =?us-ascii?Q?bpJhSA=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0tslJGv1CYYc3+LKq8JjMVF8OMhcbpHHGOK9E57EohSbxLV7OwkJxgE8TeKr7sDn2LUrgS0vo6lIKlvkuust2vrQyBjHV8iHeC8XO1qcEGNPx6Iva6X4/ZpsKUjMbxyoprij59nN0hFKiuzVHVtdvebanFH/9OoAeM39UcZzZ8oQaYcMH7+k1ZgTTj712B28AdXBqfPV/FX9Ek/V8t7d8aFEOBZTnrPY03CaFU12MTAy+PEMhMQ6Ki+30SKBwLwnbY47S4tRV6GukI5WT12dy6RFJMuuLXYMBC2xGmJfhnNpm8ly67NKstnvM1wfBVPC0QsdItQSRyiUl/uSHFGGzjGeTjP2KoFbY/P0RGZwtkN2kd8/mx5/nfuOyFfGTwfNxU+UXa5m3dU7U3DTlt8Ib78uHZT2frdfDKjbbVvpLo1rnbV+GjlercD6tUnLyi5D X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 20:43:39.6811 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 117ed158-063d-488b-24ca-08de731c39ad X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000208.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9703 From: Dragos Tatulea Adapt the rx path in SHAMPO mode to calculate page size based on configured page_shift when dealing with payload data. This is necessary as an upcoming patch will add support for using different page sizes. This change has no functional changes. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 34 ++++++++++++------- 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c index efcfcddab376..fc95ea00666b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -1847,11 +1847,14 @@ mlx5e_shampo_fill_skb_data(struct sk_buff *skb, struct mlx5e_rq *rq, struct mlx5e_frag_page *frag_page, u32 data_bcnt, u32 data_offset) { + u32 page_size = BIT(rq->mpwqe.page_shift); + net_prefetchw(skb->data); do { /* Non-linear mode, hence non-XSK, which always uses PAGE_SIZE. */ - u32 pg_consumed_bytes = min_t(u32, PAGE_SIZE - data_offset, data_bcnt); + u32 pg_consumed_bytes = min_t(u32, page_size - data_offset, + data_bcnt); unsigned int truesize = pg_consumed_bytes; mlx5e_add_skb_frag(rq, skb, frag_page, data_offset, @@ -1872,6 +1875,7 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *w u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt); struct mlx5e_frag_page *head_page = frag_page; struct mlx5e_xdp_buff *mxbuf = &rq->mxbuf; + u32 page_size = BIT(rq->mpwqe.page_shift); u32 frag_offset = head_offset; u32 byte_cnt = cqe_bcnt; struct skb_shared_info *sinfo; @@ -1926,9 +1930,9 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *w linear_hr = skb_headroom(skb); linear_data_len = headlen; linear_frame_sz = MLX5_SKB_FRAG_SZ(skb_end_offset(skb)); - if (unlikely(frag_offset >= PAGE_SIZE)) { + if (unlikely(frag_offset >= page_size)) { frag_page++; - frag_offset -= PAGE_SIZE; + frag_offset -= page_size; } } @@ -1940,7 +1944,7 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *w while (byte_cnt) { /* Non-linear mode, hence non-XSK, which always uses PAGE_SIZE. */ pg_consumed_bytes = - min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); + min_t(u32, page_size - frag_offset, byte_cnt); if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) truesize += pg_consumed_bytes; @@ -1978,7 +1982,7 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *w nr_frags_free = old_nr_frags - sinfo->nr_frags; if (unlikely(nr_frags_free)) { frag_page -= nr_frags_free; - truesize -= (nr_frags_free - 1) * PAGE_SIZE + + truesize -= (nr_frags_free - 1) * page_size + ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz)); } @@ -2166,15 +2170,16 @@ mlx5e_shampo_flush_skb(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, bool match) rq->hw_gro_data->skb = NULL; } -static bool -mlx5e_hw_gro_skb_has_enough_space(struct sk_buff *skb, u16 data_bcnt) +static bool mlx5e_hw_gro_skb_has_enough_space(struct sk_buff *skb, + u16 data_bcnt, + u32 page_size) { int nr_frags = skb_shinfo(skb)->nr_frags; - if (PAGE_SIZE >= GRO_LEGACY_MAX_SIZE) + if (page_size >= GRO_LEGACY_MAX_SIZE) return skb->len + data_bcnt <= GRO_LEGACY_MAX_SIZE; else - return PAGE_SIZE * nr_frags + data_bcnt <= GRO_LEGACY_MAX_SIZE; + return page_size * nr_frags + data_bcnt <= GRO_LEGACY_MAX_SIZE; } static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) @@ -2183,18 +2188,19 @@ static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct mlx5e_rq *rq, struct mlx5_cq u16 header_index = mlx5e_shampo_get_cqe_header_index(rq, cqe); u32 wqe_offset = be32_to_cpu(cqe->shampo.data_offset); u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); - u32 data_offset = wqe_offset & (PAGE_SIZE - 1); u32 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); u16 wqe_id = be16_to_cpu(cqe->wqe_id); - u32 page_idx = wqe_offset >> PAGE_SHIFT; u16 head_size = cqe->shampo.header_size; struct sk_buff **skb = &rq->hw_gro_data->skb; bool flush = cqe->shampo.flush; bool match = cqe->shampo.match; + u32 page_size = BIT(rq->mpwqe.page_shift); struct mlx5e_rq_stats *stats = rq->stats; struct mlx5e_rx_wqe_ll *wqe; struct mlx5e_mpw_info *wi; struct mlx5_wq_ll *wq; + u32 data_offset; + u32 page_idx; wi = mlx5e_get_mpw_info(rq, wqe_id); wi->consumed_strides += cstrides; @@ -2210,7 +2216,11 @@ static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct mlx5e_rq *rq, struct mlx5_cq goto mpwrq_cqe_out; } - if (*skb && (!match || !(mlx5e_hw_gro_skb_has_enough_space(*skb, data_bcnt)))) { + data_offset = wqe_offset & (page_size - 1); + page_idx = wqe_offset >> rq->mpwqe.page_shift; + if (*skb && + !(match && mlx5e_hw_gro_skb_has_enough_space(*skb, data_bcnt, + page_size))) { match = false; mlx5e_shampo_flush_skb(rq, cqe, match); } -- 2.44.0