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Tue, 24 Feb 2026 03:47:18 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Dragos Tatulea , Shay Drory Subject: [PATCH net 2/5] net/mlx5: LAG, disable MPESW in lag_disable_change() Date: Tue, 24 Feb 2026 13:46:49 +0200 Message-ID: <20260224114652.1787431-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260224114652.1787431-1-tariqt@nvidia.com> References: <20260224114652.1787431-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|SAWPR12MB999142:EE_ X-MS-Office365-Filtering-Correlation-Id: 251ef89d-8fd3-47dd-846e-08de739a819e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?40hGQ/4ZA9aSJS57n+hRaiVIfzlNPDiVSzeJJpQM7/yAPXskjhue3evOBnG8?= =?us-ascii?Q?DECwLwGqVWZeCVR74kNe0HKKepNFo1reSIJzdM+8+066h6sXu9q14ACVCni4?= =?us-ascii?Q?S3Mmec1R9ygYUgcrhAREXU4Lx4uFAd59MxjoHNpLnfvg5duV8/lsv6Rsq3lD?= =?us-ascii?Q?Wy9u5DCqbEY9QyZ8c/daogv2vpoKzlmDM3DIBaA6rXx7QxRboBO9ZDk7o1GW?= =?us-ascii?Q?zfn/iY+0S6OJF1JIjaFYAusCUI4NO5RTCC4bAdF2eDe3Q2ixHUAXeXbaUWUZ?= =?us-ascii?Q?bONsFLTgrBpyxpZJ6SAkNwqwBYFuRS3iNjbKLQ9HXjcU58J5XB5ZRRASr35g?= =?us-ascii?Q?6+e1ouyddVQTTUtbZ4xhdGIA1Psenxp/j2KSQB8+E3TT8CQnOhEnL3MAeaTb?= =?us-ascii?Q?oQhXJJ7DxNuCfPURZMUiyxG6Q62z7Pp8sn0jgQzFF7SCGh6K7C2UG46eCPlq?= =?us-ascii?Q?sMtTmMcPg7Vvltiy6CCErrwY1/HINHlZr5pnlri6UIsWNg99uCDthtbdi9k3?= =?us-ascii?Q?gESL51c0S22bJdOaZt96lR2cytYWICZO0iqKJAZWuMLRU6XHnlYYbmXu77xh?= =?us-ascii?Q?7wRHZ0W0uMdkk/wnEawkTshbMMBndz/YfqQDKmXl/egBghi3MNdC3KN5U05d?= =?us-ascii?Q?lbjemsdXmbbiLO8Lav73pq1HN6p4TwrULMDo17dEbsGb4Ct8WTj7ul4kXGrn?= =?us-ascii?Q?Bdx6/RS53iZ5C6RcNzMaCkHRBcD4gKidJhNlAkLx6NUMmYz0E9/wI3Vt85h4?= =?us-ascii?Q?Atc8yO+/NtblThKlHp35Ao/nU29q6ZLzGqX03n+TyDuCbwX2l5Cf9jQmu8Hm?= =?us-ascii?Q?KyONwooI07ch4tXP6uF35U2I+0VwA07G9Bz212opExYloBQjnCgb398GaJ5u?= =?us-ascii?Q?aDlqb4RmSK1uI2Rlo6Vzd5pp/15U2o0HkeskgiyJVu4FYUSgCHJ33/+Nc19q?= =?us-ascii?Q?ksS88TzRtnCIZ7HlLEs0blvegE6zxfhDuSvfUeLHxHwJKHBAwHwmkjmSfaRj?= =?us-ascii?Q?GA05Y44hT2x9Ze0dEmuawRc6PnXus3+R3UmnU3zHVNEwqykvQ0043ZUl17Fl?= =?us-ascii?Q?Jqee85PMOVLcvNiTJLtMZV2Ufvq6qRCayKYEGOqkKj+4setjEXU/Q9Nwec3J?= =?us-ascii?Q?YD5OaNSRr9CC6F4yDNOE2EV5IPqIpfSWYuXKKCjO/9mgX8jIzNgIry1Uer/4?= =?us-ascii?Q?7Bhc11lpx8ZyjzXpe/46oNC8F1bk53YCtdyGSw02b665uLkPKQNea7gfP+YN?= =?us-ascii?Q?qTH13P9byT8+ao1v7+K5JalEeRUu176RT8hkWnCDtrlC+S0DrZb4Wn6QQ+nu?= =?us-ascii?Q?gQhzJ8vMxNryATFKm/652PCmO5S4TLhqoDg8T4yLRx0UclpAvXFUTC/q0J5h?= =?us-ascii?Q?p5iDuPPJ8vOWL8Yed2/WogSGdGDmDJBha341hBHgK8D7nEp5M7aCbxe8Sqoq?= =?us-ascii?Q?ILkh+7K5OWtRO2sZAUuBlkJcvkr0yN1i7Upspw/0098O0y7vrdOaQlQkjyAW?= =?us-ascii?Q?COL/uhpsZGltvMaZHLTy1ISi/+whaNaRjYa7/Rx6NTicBy+sfDrx2FtYJ0QF?= =?us-ascii?Q?smy5dtwAce1DIsYJM93UbGZ+kGHp8tid6oFoZ051Adnjft6a8JYJtSF6stBx?= =?us-ascii?Q?/ihvKhEVTr3RLBCqJ1VJxDIWEpIvEurioxKPDnMZSeFE9hqVTi1YyV4ePoj7?= =?us-ascii?Q?hB9r3w=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: goUapB0HooW7Gm0ZONMsC79QzNA5aRL8vtyDNqxLQedBJWSsAGP0oIWSWbDm52D0NdNNUD2NGd40JnTbbuvlwQ5svGvfvN7NC+yc487purIb7BhmOfQQFbiHToUdTX+8XqHiTvrnI1j4XFaZM5dfgFK8wP8PloSwjc+2ICRJPSkyOo6irDs7hU6EFPMUcWwP7UbPKlosuEy5SAluzoLiZGILXiIBA66XwuQgF0iHKOCaXfKN6ra80ZQEjXRJxMfEtwW+Ngi+onDHM406RDrSBFDWiCw04Se30BxbUGZLYkGF3FOBrxlrayB8/OdIK93x+dKoHpjH9PGWEX7IUlyieYOl9BWizqhsIkZiswD8bvjfW6trGXk29izGjHJmihw8NCF7WeoXU97Dktty+nnX4yvArIRbHRHtYk8K6ijDZNlIAh5w5kC9iekqXj34jCBu X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2026 11:47:36.8070 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 251ef89d-8fd3-47dd-846e-08de739a819e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SAWPR12MB999142 From: Shay Drory mlx5_lag_disable_change() unconditionally called mlx5_disable_lag() when LAG was active, which is incorrect for MLX5_LAG_MODE_MPESW. Hnece, call mlx5_disable_mpesw() when running in MPESW mode. Fixes: a32327a3a02c ("net/mlx5: Lag, Control MultiPort E-Switch single FDB mode") Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c | 8 ++++++-- drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c | 8 ++++---- drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h | 5 +++++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c index 9fe47c836ebd..859f042caf79 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -1869,8 +1869,12 @@ void mlx5_lag_disable_change(struct mlx5_core_dev *dev) mutex_lock(&ldev->lock); ldev->mode_changes_in_progress++; - if (__mlx5_lag_is_active(ldev)) - mlx5_disable_lag(ldev); + if (__mlx5_lag_is_active(ldev)) { + if (ldev->mode == MLX5_LAG_MODE_MPESW) + mlx5_lag_disable_mpesw(ldev); + else + mlx5_disable_lag(ldev); + } mutex_unlock(&ldev->lock); mlx5_devcom_comp_unlock(dev->priv.hca_devcom_comp); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c index 04762562d7d9..a63d48d18878 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c @@ -65,7 +65,7 @@ static int mlx5_mpesw_metadata_set(struct mlx5_lag *ldev) return err; } -static int enable_mpesw(struct mlx5_lag *ldev) +static int mlx5_lag_enable_mpesw(struct mlx5_lag *ldev) { struct mlx5_core_dev *dev0; int err; @@ -126,7 +126,7 @@ static int enable_mpesw(struct mlx5_lag *ldev) return err; } -static void disable_mpesw(struct mlx5_lag *ldev) +void mlx5_lag_disable_mpesw(struct mlx5_lag *ldev) { if (ldev->mode == MLX5_LAG_MODE_MPESW) { mlx5_mpesw_metadata_cleanup(ldev); @@ -152,9 +152,9 @@ static void mlx5_mpesw_work(struct work_struct *work) } if (mpesww->op == MLX5_MPESW_OP_ENABLE) - mpesww->result = enable_mpesw(ldev); + mpesww->result = mlx5_lag_enable_mpesw(ldev); else if (mpesww->op == MLX5_MPESW_OP_DISABLE) - disable_mpesw(ldev); + mlx5_lag_disable_mpesw(ldev); unlock: mutex_unlock(&ldev->lock); mlx5_devcom_comp_unlock(devcom); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h index f5d9b5c97b0d..b767dbb4f457 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h @@ -31,6 +31,11 @@ int mlx5_lag_mpesw_do_mirred(struct mlx5_core_dev *mdev, bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev); void mlx5_lag_mpesw_disable(struct mlx5_core_dev *dev); int mlx5_lag_mpesw_enable(struct mlx5_core_dev *dev); +#ifdef CONFIG_MLX5_ESWITCH +void mlx5_lag_disable_mpesw(struct mlx5_lag *ldev); +#else +static inline void mlx5_lag_disable_mpesw(struct mlx5_lag *ldev) {} +#endif /* CONFIG_MLX5_ESWITCH */ #ifdef CONFIG_MLX5_ESWITCH void mlx5_mpesw_speed_update_work(struct work_struct *work); -- 2.44.0