* [PATCH net] amd-xgbe: fix MAC_TCR_SS register width for 2.5G and 10M speeds
@ 2026-02-26 17:07 Raju Rangoju
2026-02-28 22:30 ` patchwork-bot+netdevbpf
0 siblings, 1 reply; 2+ messages in thread
From: Raju Rangoju @ 2026-02-26 17:07 UTC (permalink / raw)
To: netdev
Cc: linux-kernel, pabeni, kuba, edumazet, davem, andrew+netdev,
Raju.Rangoju, Guruvendra Punugupati
Extend the MAC_TCR_SS (Speed Select) register field width from 2 bits
to 3 bits to properly support all speed settings.
The MAC_TCR register's SS field encoding requires 3 bits to represent
all supported speeds:
- 0x00: 10Gbps (XGMII)
- 0x02: 2.5Gbps (GMII) / 100Mbps
- 0x03: 1Gbps / 10Mbps
- 0x06: 2.5Gbps (XGMII) - P100a only
With only 2 bits, values 0x04-0x07 cannot be represented, which breaks
2.5G XGMII mode on newer platforms and causes incorrect speed select
values to be programmed.
Fixes: 07445f3c7ca1 ("amd-xgbe: Add support for 10 Mbps speed")
Co-developed-by: Guruvendra Punugupati <Guruvendra.Punugupati@amd.com>
Signed-off-by: Guruvendra Punugupati <Guruvendra.Punugupati@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
drivers/net/ethernet/amd/xgbe/xgbe-common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
index 711f295eb777..80c2c27ac9dc 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
@@ -431,7 +431,7 @@
#define MAC_SSIR_SSINC_INDEX 16
#define MAC_SSIR_SSINC_WIDTH 8
#define MAC_TCR_SS_INDEX 29
-#define MAC_TCR_SS_WIDTH 2
+#define MAC_TCR_SS_WIDTH 3
#define MAC_TCR_TE_INDEX 0
#define MAC_TCR_TE_WIDTH 1
#define MAC_TCR_VNE_INDEX 24
--
2.34.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH net] amd-xgbe: fix MAC_TCR_SS register width for 2.5G and 10M speeds
2026-02-26 17:07 [PATCH net] amd-xgbe: fix MAC_TCR_SS register width for 2.5G and 10M speeds Raju Rangoju
@ 2026-02-28 22:30 ` patchwork-bot+netdevbpf
0 siblings, 0 replies; 2+ messages in thread
From: patchwork-bot+netdevbpf @ 2026-02-28 22:30 UTC (permalink / raw)
To: Raju Rangoju
Cc: netdev, linux-kernel, pabeni, kuba, edumazet, davem,
andrew+netdev, Guruvendra.Punugupati
Hello:
This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Thu, 26 Feb 2026 22:37:53 +0530 you wrote:
> Extend the MAC_TCR_SS (Speed Select) register field width from 2 bits
> to 3 bits to properly support all speed settings.
>
> The MAC_TCR register's SS field encoding requires 3 bits to represent
> all supported speeds:
> - 0x00: 10Gbps (XGMII)
> - 0x02: 2.5Gbps (GMII) / 100Mbps
> - 0x03: 1Gbps / 10Mbps
> - 0x06: 2.5Gbps (XGMII) - P100a only
>
> [...]
Here is the summary with links:
- [net] amd-xgbe: fix MAC_TCR_SS register width for 2.5G and 10M speeds
https://git.kernel.org/netdev/net/c/9439a661c2e8
You are awesome, thank you!
--
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2026-02-26 17:07 [PATCH net] amd-xgbe: fix MAC_TCR_SS register width for 2.5G and 10M speeds Raju Rangoju
2026-02-28 22:30 ` patchwork-bot+netdevbpf
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