From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [207.46.229.174]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 633852DCBEC; Tue, 3 Mar 2026 06:16:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=207.46.229.174 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772518570; cv=none; b=nyAYiq38yK4LBnqCul1GM5UEEMpdNBI6K3ZQNkLhC9Uc3wtXtYia16f2x3lSSEg+zGW/PUw0NyTYmDwa7r6Rk1Q9YBH9+v77xMVY0RByT3AAWb/WaImYO0Vx2AE/bSsP92+olWfIcs2ngdTf7sww9k0CTQ82aE+GOkpRwA6/y90= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772518570; c=relaxed/simple; bh=eSNUqfeb+9+NO8GVgejZ3lkjPrPxheNL4AgfVdI1ImY=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=tG2NYaf6UPfhtDtPK+QGwPVUxzPXPKUuT5ao/7k4SFrGd6E/bFq+gZ1SLGiCuZhvlRcP/tWGg5lYKk30qRJzk18Gr4I4gTwGSkYWun+0U58prnAl39uDuLUvMMlFGRnWghpugp2Cf6ZOIr1enrdE1FgVii8ZrCp57iEIFyqAJqw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=207.46.229.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0004057DT.eswin.cn (unknown [10.11.96.26]) by app1 (Coremail) with SMTP id TAJkCgCXLHGBfKZpcToFAA--.18321S2; Tue, 03 Mar 2026 14:15:31 +0800 (CST) From: lizhi2@eswincomputing.com To: devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, wens@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com, Zhi Li Subject: [PATCH net-next v3 0/3] net: stmmac: eic7700: fix EIC7700 eth1 RX sampling timing Date: Tue, 3 Mar 2026 14:15:24 +0800 Message-ID: <20260303061525.846-1-lizhi2@eswincomputing.com> X-Mailer: git-send-email 2.52.0.windows.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:TAJkCgCXLHGBfKZpcToFAA--.18321S2 X-Coremail-Antispam: 1UD129KBjvJXoWxXF4UWF1UAr1kWFWkJrW8JFb_yoWrJF1UpF W5Wr4agF1DJr1xJwsFq3W0934rJan3G3W7ur18Jrn7JwsI9Fn0qrW2kF15XFy8CrZ7uryU AFy5Ka1UCa4j9rJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBv14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0pRBOJnUUUUU= X-CM-SenderInfo: xol2xx2s6h245lqf0zpsxwx03jof0z/ From: Zhi Li v2 -> v3: - Update eswin,eic7700-eth.yaml: - Extend rx-internal-delay-ps and tx-internal-delay-ps range from 0-2400 to 0-2540 to match the full 7-bit hardware delay field (127 * 20 ps). - Add "multipleOf: 20" constraint to reflect the 20 ps hardware step size. - Make rx-internal-delay-ps and tx-internal-delay-ps optional. A well-designed board should not require internal delay tuning. - Remove rx-internal-delay-ps and tx-internal-delay-ps from the example to avoid encouraging blind copy into board DTs. - Update dwmac-eic7700.c: - Treat rx-internal-delay-ps and tx-internal-delay-ps as optional DT properties. - Apply delay configuration only when properties are present. - Keep TX/RX delay registers cleared by default to ensure a deterministic state when no delay is specified. - Describe Ethernet configuration for the HiFive Premier P550 board: - Add GMAC controller nodes for the HiFive Premier P550 board to describe the on-board Ethernet configuration. The Ethernet controller depends on clock, reset, pinctrl and HSP subsystem providers which are currently under upstream review. These dependent nodes will be submitted separately once the corresponding drivers are merged. Due to these missing dependencies, dt-binding-check may report warnings or failures for this series. - No functional changes to RX clock inversion logic. - Link to v2: https://lore.kernel.org/lkml/20260209094628.886-1-lizhi2@eswincomputing.com/ - This series is based on the EIC7700 clock support series: https://lore.kernel.org/all/20260210095008.726-1-dongxuyang@eswincomputing.com/ The clock series is currently under review. v1 -> v2: - Update eswin,eic7700-eth.yaml: - Drop the vendor-specific properties eswin,rx-clk-invert and eswin,tx-clk-invert. - Introduce a distinct compatible string "eswin,eic7700-qos-eth-clk-inversion" to describe MAC instances that require internal RGMII clock inversion. This models the SoC-specific hardware difference directly via the compatible string and avoids per-board configuration properties. - Change rx-internal-delay-ps and tx-internal-delay-ps from enum to minimum/maximum to reflect the actual delay range (0-2400 ps) - Add reference to High-Speed Subsystem documentation in eswin,hsp-sp-csr description. The HSP CSR block is described in Chapter 10 ("High-Speed Interface") of the EIC7700X SoC Technical Reference Manual, Part 4 (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf): https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases - Update dwmac-eic7700.c: - Remove handling of eswin,rx-clk-invert and eswin,tx-clk-invert properties. - Select RX clock inversion based on the new "eswin,eic7700-qos-eth-clk-inversion" compatible string, using match data to apply the required configuration for affected MAC instances (eth1). - Link to v1: https://lore.kernel.org/lkml/20260109080601.1262-1-lizhi2@eswincomputing.com/ Zhi Li (3): dt-bindings: ethernet: eswin: add clock sampling control net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller .../bindings/net/eswin,eic7700-eth.yaml | 75 ++++++-- .../dts/eswin/eic7700-hifive-premier-p550.dts | 50 +++++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 54 ++++++ .../ethernet/stmicro/stmmac/dwmac-eic7700.c | 180 +++++++++++++----- 4 files changed, 300 insertions(+), 59 deletions(-) -- 2.25.1