From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from zg8tmtyylji0my4xnjeumjiw.icoremail.net (zg8tmtyylji0my4xnjeumjiw.icoremail.net [162.243.161.220]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 87A2018BBAE; Tue, 3 Mar 2026 06:17:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.161.220 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772518629; cv=none; b=V/UKmPgUybPU/Uk4A8qj/h5ZgrUGyUDy17FPv7cfuSVe/h+JXLi1iVjz2okkvBX9mxcLndzK0ccWefFCqXslPDU45wlV5H8RtHhVNBTxQiPZOVMf42nbFQk6m1qlCkQ+LU66uhWKeZCzQgvDPDOlI9Zs9sawXYMo7ZClECiyy90= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772518629; c=relaxed/simple; bh=3i/0eEzdnHOtJJyA50sIWua4TIWR9ravZnOlYxvWB8s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hRMd78+b8KzD1V70cNqV/0yfCoScPC2LfQD+rg0v+N7Ke4dr3Jte5G5MlsrQFkOqOdbls7+p3E0b9Loi2p4eVVnyzdAjntmB5lk4IJJsL1iu43e4fqv3rkBu5t5izLv12yPAfaWxihCdPzNgjeGdke0hYRfSiDUy2xvvK4a6T5Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=162.243.161.220 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0004057DT.eswin.cn (unknown [10.11.96.26]) by app2 (Coremail) with SMTP id TQJkCgD3DKDIfKZpeTgFAA--.23975S2; Tue, 03 Mar 2026 14:16:41 +0800 (CST) From: lizhi2@eswincomputing.com To: devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, wens@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com, Zhi Li Subject: [PATCH net-next v3 1/3] dt-bindings: ethernet: eswin: add clock sampling control Date: Tue, 3 Mar 2026 14:16:37 +0800 Message-ID: <20260303061637.872-1-lizhi2@eswincomputing.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260303061525.846-1-lizhi2@eswincomputing.com> References: <20260303061525.846-1-lizhi2@eswincomputing.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:TQJkCgD3DKDIfKZpeTgFAA--.23975S2 X-Coremail-Antispam: 1UD129KBjvJXoW3JFW5GF43AFyUCryxAF4xWFg_yoWxXw1UpF W5C3y3Grn8Xr1fZa17tF10ka4ftws3WF13Crn7t3Z7Xws0qrWYqr47tFyrGa48Cr4xZFy5 WFWYga18ua4vk3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRimiiDUUUU X-CM-SenderInfo: xol2xx2s6h245lqf0zpsxwx03jof0z/ From: Zhi Li The second Ethernet controller (eth1) on the EIC7700 SoC may experience RX data sampling issues at high speed due to EIC7700-specific receive clock to data skew at the MAC input. On the EIC7700 SoC, the second Ethernet controller (eth1) requires inversion of the internal RGMII receive clock in order to meet RX data sampling timing at high speed. Describe this SoC-specific difference by introducing a distinct compatible string for MAC instances that require internal clock inversion, allowing the driver to select the appropriate configuration without relying on per-board vendor-specific properties. The rx-internal-delay-ps and tx-internal-delay-ps properties now use minimum and maximum constraints to reflect the actual hardware delay range (0-2540 ps) applied in 20 ps steps. This relaxes the binding validation compared to the previous enum-based definition and avoids regressions for existing DTBs while keeping the same hardware limits. Treat the RX/TX internal delay properties as optional, board-specific tuning knobs and remove them from the example to avoid encouraging their use. In addition, the binding now includes additional background information about the HSP CSR registers accessed by the MAC. The TXD and RXD delay control registers are included so the driver can explicitly clear any residual configuration left by the bootloader. Background reference for the High-Speed Subsystem and HSP CSR block is available in Chapter 10 ("High-Speed Interface") of the EIC7700X SoC Technical Reference Manual, Part 4 (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf): https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases There are currently no in-tree users of the EIC7700 Ethernet driver, so these changes are safe. Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC") Signed-off-by: Zhi Li --- .../bindings/net/eswin,eic7700-eth.yaml | 75 +++++++++++++++---- 1 file changed, 59 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml index 91e8cd1db67b..22d1cecea07e 100644 --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -20,6 +20,7 @@ select: contains: enum: - eswin,eic7700-qos-eth + - eswin,eic7700-qos-eth-clk-inversion required: - compatible @@ -28,9 +29,13 @@ allOf: properties: compatible: - items: - - const: eswin,eic7700-qos-eth - - const: snps,dwmac-5.20 + oneOf: + - items: + - const: eswin,eic7700-qos-eth + - const: snps,dwmac-5.20 + - items: + - const: eswin,eic7700-qos-eth-clk-inversion + - const: snps,dwmac-5.20 reg: maxItems: 1 @@ -63,16 +68,29 @@ properties: - const: stmmaceth rx-internal-delay-ps: - enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + minimum: 0 + maximum: 2540 + multipleOf: 20 tx-internal-delay-ps: - enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + minimum: 0 + maximum: 2540 + multipleOf: 20 eswin,hsp-sp-csr: description: HSP CSR is to control and get status of different high-speed peripherals (such as Ethernet, USB, SATA, etc.) via register, which can tune board-level's parameters of PHY, etc. + + Additional background information about the High-Speed Subsystem + and the HSP CSR block is available in Chapter 10 ("High-Speed Interface") + of the EIC7700X SoC Technical Reference Manual, Part 4 + (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is + publicly available at + https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases + + This reference is provided for background information only. $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: @@ -81,7 +99,9 @@ properties: or external clock selection - description: Offset of AXI clock controller Low-Power request register + - description: Offset of register controlling TXD delay - description: Offset of register controlling TX/RX clock delay + - description: Offset of register controlling RXD delay required: - compatible @@ -93,8 +113,6 @@ required: - phy-mode - resets - reset-names - - rx-internal-delay-ps - - tx-internal-delay-ps - eswin,hsp-sp-csr unevaluatedProperties: false @@ -104,24 +122,49 @@ examples: ethernet@50400000 { compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20"; reg = <0x50400000 0x10000>; + interrupt-parent = <&plic>; + interrupts = <61>; + interrupt-names = "macirq"; clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, <&d0_clock 193>; clock-names = "axi", "cfg", "stmmaceth", "tx"; + resets = <&reset 95>; + reset-names = "stmmaceth"; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x114 0x118 0x11c>; + phy-handle = <&gmac0_phy0>; + phy-mode = "rgmii-id"; + snps,aal; + snps,fixed-burst; + snps,tso; + snps,axi-config = <&stmmac_axi_setup_gmac0>; + + stmmac_axi_setup_gmac0: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <2>; + snps,wr_osr_lmt = <2>; + }; + }; + + ethernet@50410000 { + compatible = "eswin,eic7700-qos-eth-clk-inversion", "snps,dwmac-5.20"; + reg = <0x50410000 0x10000>; interrupt-parent = <&plic>; - interrupts = <61>; + interrupts = <70>; interrupt-names = "macirq"; - phy-mode = "rgmii-id"; - phy-handle = <&phy0>; - resets = <&reset 95>; + clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, + <&d0_clock 194>; + clock-names = "axi", "cfg", "stmmaceth", "tx"; + resets = <&reset 94>; reset-names = "stmmaceth"; - rx-internal-delay-ps = <200>; - tx-internal-delay-ps = <200>; - eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>; - snps,axi-config = <&stmmac_axi_setup>; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x214 0x218 0x21c>; + phy-handle = <&gmac1_phy0>; + phy-mode = "rgmii-id"; snps,aal; snps,fixed-burst; snps,tso; - stmmac_axi_setup: stmmac-axi-config { + snps,axi-config = <&stmmac_axi_setup_gmac1>; + + stmmac_axi_setup_gmac1: stmmac-axi-config { snps,blen = <0 0 0 0 16 8 4>; snps,rd_osr_lmt = <2>; snps,wr_osr_lmt = <2>; -- 2.25.1