Re: [PATCH net-next v2 1/3] net: macb: fix SGMII with inband aneg disabled

[Conor Dooley <conor@kernel.org>]

[-- Attachment #1: Type: text/plain, Size: 1605 bytes --]

On Thu, Mar 05, 2026 at 02:28:08PM +0000, Russell King (Oracle) wrote:
> On Thu, Mar 05, 2026 at 02:13:24PM +0000, Conor Dooley wrote:
> > On Thu, Mar 05, 2026 at 05:56:15AM -0800, Charles Perry wrote:
> > > On Thu, Mar 05, 2026 at 09:42:19AM +0000, Conor Dooley wrote:
> > > > On Wed, Mar 04, 2026 at 09:37:23AM -0800, Charles Perry wrote:
> > > > > On Wed, Mar 04, 2026 at 04:23:30PM +0000, Conor Dooley wrote:
> > > > > 
> > > > > Are you able to check register 23, bit 13 of your PHY by any chance? Maybe
> > > > > with the mdio/mii commands in U-Boot if you have that.
> > > > 
> > > > "mii read addr 23" returns 0660 for both PHYs in U-Boot.
> > > 
> > > Oh, I think you fell into a trap of U-Boot's mii command.
> > > 
> > > The arguments are always in hex even if you dont prepend "0x".
> > 
> > Eh no, actually I thought that you meant register 0x23. I'm not used to
> > register addresses being given in decimal.
> > 
> > > What "mii read 8 23" did is most likely read register 0x23, masked with
> > > 0x1f because clause 22 has only 32 registers. So it read register 0x3 which
> > > is the device identifier 2 register: 0x0660.
> > > 
> > > The exact command should be "mii read 8 0x17", "mii read 9 0x17".
> > 
> > Both read back 2004
> 
> It would would be good to see the content of 0x1b, specifically bit 13.
> The PHY supports AN bypass, and I suspect bit 13 is zero, which means
> in combination with bit 13 set in 0x17, the PHY must complete the SGMII
> exchange with the MAC.

They're both 0401, so yea. I'll give the vitesse driver change a go
later.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]