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Sat, 7 Mar 2026 22:56:22 -0800 From: Tariq Toukan To: Leon Romanovsky , Jason Gunthorpe , "Saeed Mahameed" , Tariq Toukan CC: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , Mark Bloch , , , , Gal Pressman , Dragos Tatulea , Moshe Shemesh , Shay Drory , Alexei Lazar Subject: [PATCH mlx5-next 0/8] mlx5-next updates 2026-03-08 Date: Sun, 8 Mar 2026 08:55:51 +0200 Message-ID: <20260308065559.1837449-1-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002318:EE_|IA1PR12MB8407:EE_ X-MS-Office365-Filtering-Correlation-Id: 13155311-db56-4ea0-45c9-08de7cdfd8a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|7416014|82310400026|376014; X-Microsoft-Antispam-Message-Info: X0lRjM+CfMDj78HvtPrCaYT8bTs9G9FX24BPtHXX7ZAAAPzVQcGIszgkWGbFRqctYcGn/25dXsL3oVFsqYNv3dSBauWUkb4oWDXWNWSQEQdWk+2CvAHglkyqA17KXyv7yhW3a5bDnHuzp58hEd+jJSKt/LuV6qIG9omUQ60ly/myL8pu/IIXU/YWFkFJSWDfiubeqog6TuY5dfFhFGeA6o1pMsApFr6mq8NVKSZOOXw1G7qZvgWIeg0p1S0E2mlTLl6GOgVVGh+JsholhxAYCol0GOJfYQMgJLeZcK8q83l3JELiup/TtDoZyPYNTW2KaY1hK+f1TLycTv00EgnuinGp6zyW7MyARCGv2P3Gt1zpyJProP6N3zfnl07HE0yN7V7E2WBxyQ9p/Zvhl5fL/x71zPRgxgB5ezyxmYd6Zx1+Tfm4SyUffZLV3mfuURhms7oScH4KXv92axzxw4N+RLJl61ihfK0VU2rJ3q4TnemKfckSytmjXlH6jG1yM3fQYLYN4PsBR5oDA2z1WhQsbTU5jbHRlSvSRsOqQIiz4PpFhAyHQs2szjquj7zZe+64JWZKmMJp2umm0GkK09wqiY2lRpaasnZB/67sw2UROSb/QWjz8HXsWhrHj1wZQLe2g1n35UmNqcw2hcHKfsnf1dYH5jGxXUVoqpbuDueBMZmvmNzi3Y6adqEjZdZLrx8NTDdD+NVprZUXXKSGUyon/ZnXVIlbCDGNzmqpSBT3W1nErud0ZBLZtW7T94hwrNCs0euaXpkYviqeN7RIGNRA4A== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(7416014)(82310400026)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: m2xqJmhWv0v3R+dMzEF2uvKbyuqfPm0J5Sx4ULy6KjfRw7kFTycqLnklgxcm5ZH1HPdbaBrwauM65J9luGJwIWmJrUICZuJv5AOVlVMrAUtXKi5RQ/+l+rjiN8CVYyEaSbHBA8fFkxqBLwJoB0ndNhSoiXfXEyPj5wZN2pUlSgpS2L/iVU0DzdP/PIB1nv90uAFt5D9C2F5/MlGvkHJvCw0vFTM5z113/GQVc8+zYzxMpydi/TIhColy4sfixYqQe2N1E1dSCuU5bZaxJRUgwiZeQQY7SA1d+7RuekC4Qyv0Q6YJdrikRNn3kUJH5UdyQf5LpkGmE+qrZAyA+uY82vVbTfujRK4/ZH5JdE5Xx8Z87jd2AkVRkthKyt0wk2QWl3PiU3yVblS7l5PoLoNs7avT+qujPO++dnaF/W4eyQB6s3ix8TNaf1ICiQXJJVDi X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Mar 2026 06:56:38.7375 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13155311-db56-4ea0-45c9-08de7cdfd8a6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8407 Hi, This series contains mlx5 shared updates as preparation for upcoming features. First patch by Alex contains IFC changes as preparation for an upcoming feature. Patches 2 and up by Shay introduce mlx5 infrastructure for SD switchdev and LAG support. Detailed description by Shay below. Regards, Tariq This series adds shared infrastructure to enable Socket Direct (SD) single-netdev switchdev transition and LAG support in subsequent patches. Currently, LAG is not supported in Socket Direct configurations, and BlueField-3/4 utilizing SD for North-South traffic operates with two distinct eSwitches per physical port. This forces the use of separate IPs and MAC addresses for each NUMA node, complicating network configuration and requiring firmware to handle MPFS with different inner and outer packets for communication. The goal is to expose a single external IP address (single MAC address) per physical port while maintaining SD's bandwidth and latency benefits. This means having a single eswitch per physical port managing all physical ports via merged eswitch with multiple vports. This enables single FDB creation which will result in a single RDMA device to be used by DOCA/HWS/OVS. To achieve this, the LAG infrastructure needs changes since the current implementation assumes a fixed mapping between device indices and LAG ports, which breaks with SD's multi-device-per-port model. This series prepares the groundwork by: 1. Adding IFC bits for silent mode query and VHCA RX destination type, needed for SD device coordination and cross-VHCA traffic steering. 2. Converting the LAG pf array to xarray and using xa_alloc for dynamic index management. This decouples LAG indexing from physical device indices, allowing flexible device membership. 3. Convert peer_miss_rule array to xarray, key with vhca_id. 4. Introducing LAG variant of device index helpers that produce unique identifiers even when multiple devices share the same physical port. 5. Adding VHCA RX flow destination support for steering traffic to a specific VHCA's receive path. 6. Moving LAG demux table ownership to the LAG layer with APIs for SW-only LAG modes where firmware cannot create the demux table. A follow-up series will build on this infrastructure to implement: - SD single-netdev switchdev mode transition with shared FDB corresponded to the SD group. - LAG support enabling bonding of SD groups Since the follow-up series is large (~20 patches), the shared code between RDMA and net is sent in advance to avoid overloading the shared branch tree. Alexei Lazar (1): net/mlx5: Add IFC bits for shared headroom pool PBMC support Shay Drory (6): net/mlx5: Add silent mode set/query and VHCA RX IFC bits net/mlx5: LAG, replace pf array with xarray net/mlx5: E-switch, modify peer miss rule index to vhca_id net/mlx5: LAG, replace mlx5_get_dev_index with LAG sequence number net/mlx5: Add VHCA RX flow destination support for FW steering {net/RDMA}/mlx5: Add LAG demux table API and vport demux rules Tariq Toukan (1): net/mlx5: LAG, use xa_alloc to manage LAG device indices drivers/infiniband/hw/mlx5/ib_rep.c | 24 +- drivers/infiniband/hw/mlx5/main.c | 21 +- drivers/infiniband/hw/mlx5/mlx5_ib.h | 1 - .../mellanox/mlx5/core/diag/fs_tracepoint.c | 3 + .../net/ethernet/mellanox/mlx5/core/en_tc.c | 9 +- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 14 +- .../mellanox/mlx5/core/eswitch_offloads.c | 103 ++- .../net/ethernet/mellanox/mlx5/core/fs_cmd.c | 6 +- .../net/ethernet/mellanox/mlx5/core/fs_core.c | 17 +- .../ethernet/mellanox/mlx5/core/lag/debugfs.c | 3 +- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 684 ++++++++++++++---- .../net/ethernet/mellanox/mlx5/core/lag/lag.h | 49 +- .../net/ethernet/mellanox/mlx5/core/lag/mp.c | 20 +- .../ethernet/mellanox/mlx5/core/lag/mpesw.c | 15 +- .../mellanox/mlx5/core/lag/port_sel.c | 28 +- .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 2 +- include/linux/mlx5/fs.h | 10 +- include/linux/mlx5/lag.h | 21 + include/linux/mlx5/mlx5_ifc.h | 26 +- 19 files changed, 849 insertions(+), 207 deletions(-) create mode 100644 include/linux/mlx5/lag.h base-commit: 385a06f74ff7a03e3fb0b15fb87cfeb052d75073 -- 2.44.0