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Sat, 7 Mar 2026 22:56:26 -0800 From: Tariq Toukan To: Leon Romanovsky , Jason Gunthorpe , "Saeed Mahameed" , Tariq Toukan CC: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , Mark Bloch , , , , Gal Pressman , Dragos Tatulea , Moshe Shemesh , Shay Drory , Alexei Lazar Subject: [PATCH mlx5-next 1/8] net/mlx5: Add IFC bits for shared headroom pool PBMC support Date: Sun, 8 Mar 2026 08:55:52 +0200 Message-ID: <20260308065559.1837449-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260308065559.1837449-1-tariqt@nvidia.com> References: <20260308065559.1837449-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002318:EE_|DM4PR12MB7526:EE_ X-MS-Office365-Filtering-Correlation-Id: 0429953c-ab7c-4610-844d-08de7cdfdc8a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: C2Fr7KYNLforKtEFJYMdbqITKN0bwmcegPDFvA6mAAHitkCZcqU4Khlugzg4lDHyaFZrpd8ncx0gfFSt9AHXGrh8Jv+x7/bSzEabbVaKDxycuFMOfPnVXHKZnAwfVsyksWQtBEUq+8Vm9ocJRTgATYeFC50bqa3i8BvDCa2CSuT+rMka9fGyYREVxMnAgksr9a4YYOzZGQ1mRm5ggyqfG7rfzMeHmmrzjC/AV0g81/8MwNieOwYHdOFG6o+DeN5ecUurG3hnGKgFf4C8dH09gJ4Dd5cRkKrPHLZX0kR+50xpbn0B+ckUZpUkKvnfOrg6PG8wXFjctDJBSkaVro7lXPO/WDbAP9Fa8kh4kjR0cY0Omdr8zdI6RQ/DKb66sKydHdFnJmWELjsl1H24z3ad0vjOjNjmiHUi3AGMmysJcwyX4FrvXrLAbKtKhPi0wWV6U45IuS55c4EFv4J5Ht4vH/WVTqVarA034Ej6bAIZ543kIACka0E+DLK1j9Ns4o9mPjZ61gTISq2DzzdjSfIiMAPwKspryWd8WVDQFQ4rzw9TDtAwntuSS583zIR18CuIFm5SxZyFHpYbxu8oFzZ9Kqnx39Km4ZboKIcbC9x46bJjzkAZFd9h8vLmbgSSWbYnRFVtevNpNxjolWrBamnwlKuLvyKlNUqr9nuehbhyWNBMG2gKUnviN7wZVqu0RCqzQ0ASLcIGDa/8XWB4bLl33uj68zdIE5PDeayP92RNA7zkIi8gJge8M7tFvefqCjBnUrL3vofAW0G/Se67918Rzg== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(376014)(7416014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vIlnLXqNw2V+kT08+R1F4fwcB1y/PS9FfLvOzd7IhhOP+L5wDKGesjzVDhtPQn5I7QWhWgoLDxbrplTT1HiPLR2nn+nY6S3I5vO4qzFkYQT/A77RIUrWcnP9YqXkUOZM+fiM4JCIDFUIgJ5esyiBlISUIo9ZhTEP+S72ihaabzpwZTIZBHSqvuz0U5VAZGnWpoUmhTPX2DWyIe0h+evy5OvpTqWJ0jHqiC4n9yj7DNkpMWbxk2jrRUyLfrn2Uoyz5rAoMtAQ2H4+GAdBFK4dVmcQxfcEkgaalTOSNxCIyWbOlXYAtcXX7IDej6fYehicdrxJmHeWzGdzWiqDRC3hZqmDUT7WQunkvd75NeepJJKbZPPyYZAIU2jaxtm50kTQS/DVRXvN8B9TWwY5DgsOi+9na9V7da7SHr4UlS3ahnCvy9b48JaxHT0Vko/1Uwte X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Mar 2026 06:56:45.2601 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0429953c-ab7c-4610-844d-08de7cdfdc8a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7526 From: Alexei Lazar Add hardware interface definitions for shared headroom pool (SHP) in port buffer management: - shp_pbmc_pbsr_support: capability bit in PCAM enhanced features indicating device support for shared headroom pool in PBMC/PBSR. - shared_headroom_pool: buffer entry in PBMC register (pbmc_reg_bits) for the shared headroom pool configuration, reusing the bufferx layout; reduce trailing reserved region accordingly. Signed-off-by: Alexei Lazar Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index a3948b36820d..a76c54bf1927 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -10845,7 +10845,9 @@ struct mlx5_ifc_pcam_enhanced_features_bits { u8 fec_200G_per_lane_in_pplm[0x1]; u8 reserved_at_1e[0x2a]; u8 fec_100G_per_lane_in_pplm[0x1]; - u8 reserved_at_49[0xa]; + u8 reserved_at_49[0x2]; + u8 shp_pbmc_pbsr_support[0x1]; + u8 reserved_at_4c[0x7]; u8 buffer_ownership[0x1]; u8 resereved_at_54[0x14]; u8 fec_50G_per_lane_in_pplm[0x1]; @@ -12090,8 +12092,9 @@ struct mlx5_ifc_pbmc_reg_bits { u8 port_buffer_size[0x10]; struct mlx5_ifc_bufferx_reg_bits buffer[10]; + struct mlx5_ifc_bufferx_reg_bits shared_headroom_pool; - u8 reserved_at_2e0[0x80]; + u8 reserved_at_320[0x40]; }; struct mlx5_ifc_sbpr_reg_bits { -- 2.44.0