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Sat, 7 Mar 2026 22:56:30 -0800 From: Tariq Toukan To: Leon Romanovsky , Jason Gunthorpe , "Saeed Mahameed" , Tariq Toukan CC: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , Mark Bloch , , , , Gal Pressman , Dragos Tatulea , Moshe Shemesh , Shay Drory , Alexei Lazar Subject: [PATCH mlx5-next 2/8] net/mlx5: Add silent mode set/query and VHCA RX IFC bits Date: Sun, 8 Mar 2026 08:55:53 +0200 Message-ID: <20260308065559.1837449-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260308065559.1837449-1-tariqt@nvidia.com> References: <20260308065559.1837449-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231B:EE_|SJ1PR12MB6171:EE_ X-MS-Office365-Filtering-Correlation-Id: 73af0f03-bbee-4da0-5802-08de7cdfdf02 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700016; X-Microsoft-Antispam-Message-Info: o83s+72hN25sOfw5a3IpXHe7c/azeSjDrIV7ADjZSJSVQupR+Gyjn6gPgaQh6SY1Gh0zymMVq5sQVAdRfz0dqUWXrvn76Sld3RbyezmdXTZd2kiIScZ9NHsTWc/BYNbNl+58uNFeCFnQoiJAC4PeQlKZsSujXOOA4jwv5FAlnob1atLC8JV1tKOnsKyJMHLqHWksm4u2HRF8A5W1/E0OQ7j297RnVyIqSf5IEbJ+Tevgy7ggRRIaj7BWQpKJQmTsXheTIMYvSv+FkXFHMTe8G0D42VYYbHEBbfuAtUb9ZkSjxabOGemv6myhk55JpxDT3/PQfCC2Oxnhof6WExfKt1vki24rD8qPEC328t6vC0EndQWc/+eGRwQvjCdX1DaQ1Se3Eorkx11vs4JY/a7NYbUpmyVRFk9xmE01POiNqb2aGk5uEKOXvSxXCn01Y5CaSaohnX8Cu0ozGOUdSU8Y3WkUmiKldfwMc8xvYNuOEywLepfbuk31gXiF1phjHcMaIF1gBYxFLIvee5P2KcjfEevDzkxfIFVqSOJ6zPf3M0mceL8UWwZzq02DyGAuEW7HkRALdaCIFqRzHzVMY87E/3RMGQ9cb7Ss8fNbjnMaYAXAKPKE0OTCuFxoi9W7WQk6p+WrEfzhK3Wipdn6PRxHpN1XALPOWk1mDpkUUnOSM7LW+GOfY+Pbovurq12Czg2XQSCa+5/mkkie3xB327hCr+T5LWdFsbvn0ARRbESY0UO2eAzGzBbuzJzWlczTAIBKha7ZYeyyxflfxsi0QjaRfg== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700016);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DUHZSV22qnHT122zrbpughNQeOkjN9MvNuVJg2/kryG3aOXhQH/wM2oTh16MeVqNy05TuWR2UrF2sEEbc9CwpsxJeoZ2oduUue6teEHiCkHywxQuJo+GdmN3iujnP9zISHCBJ1PXlviTNc6Z0HB5ySFU3qfCOzxy5mYKZeVRDAej/flzO+6cCfeklxA2HKziZDXqKZNcjarmK8IZd73CEIN79TGZ6Xe1C6bHZrJNzwlhiQQlLixuaS5DO8iNVxgG49XBeLlf87SZ1fnmm0FfkNh3HjqtprU7UA+YZC6ApIEUBjOqfC72j6FR12riZjF6DJO9BAK8bqUwhhXTgSOMMH/oi0hgEH7T1x+sRyDPL5WwqT9lT/sMgab4aFwrdGfXZJ52Ean5JHQ+Xp/n1+bVmtMXKthxJVV/NNKLxg/cqR96GwmeCT2Z6LflIR2DumwA X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Mar 2026 06:56:49.3980 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73af0f03-bbee-4da0-5802-08de7cdfdf02 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6171 From: Shay Drory Update the mlx5 IFC headers with newly defined capability and command-layout bits: - Add silent_mode_query and rename silent_mode to silent_mode_set cap fields. - Add forward_vhca_rx and MLX5_IFC_FLOW_DESTINATION_TYPE_VHCA_RX. - Expose silent mode fields in the L2 table query command structures. Update the SD support check to use the new capability name (silent_mode_set) to match the updated IFC definition. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/fs_cmd.c | 2 +- .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 2 +- include/linux/mlx5/mlx5_ifc.h | 19 ++++++++++++++----- 3 files changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c index c348ee62cd3a..16b28028609d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c @@ -1183,7 +1183,7 @@ int mlx5_fs_cmd_set_l2table_entry_silent(struct mlx5_core_dev *dev, u8 silent_mo { u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {}; - if (silent_mode && !MLX5_CAP_GEN(dev, silent_mode)) + if (silent_mode && !MLX5_CAP_GEN(dev, silent_mode_set)) return -EOPNOTSUPP; MLX5_SET(set_l2_table_entry_in, in, opcode, MLX5_CMD_OP_SET_L2_TABLE_ENTRY); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c index 954942ad93c5..762c783156b4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -107,7 +107,7 @@ static bool mlx5_sd_is_supported(struct mlx5_core_dev *dev, u8 host_buses) /* Disconnect secondaries from the network */ if (!MLX5_CAP_GEN(dev, eswitch_manager)) return false; - if (!MLX5_CAP_GEN(dev, silent_mode)) + if (!MLX5_CAP_GEN(dev, silent_mode_set)) return false; /* RX steering from primary to secondaries */ diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index a76c54bf1927..8fa4fb3d36cf 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -469,7 +469,8 @@ struct mlx5_ifc_flow_table_prop_layout_bits { u8 table_miss_action_domain[0x1]; u8 termination_table[0x1]; u8 reformat_and_fwd_to_table[0x1]; - u8 reserved_at_1a[0x2]; + u8 forward_vhca_rx[0x1]; + u8 reserved_at_1b[0x1]; u8 ipsec_encrypt[0x1]; u8 ipsec_decrypt[0x1]; u8 sw_owner_v2[0x1]; @@ -2012,12 +2013,14 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 disable_local_lb_mc[0x1]; u8 log_min_hairpin_wq_data_sz[0x5]; u8 reserved_at_3e8[0x1]; - u8 silent_mode[0x1]; + u8 silent_mode_set[0x1]; u8 vhca_state[0x1]; u8 log_max_vlan_list[0x5]; u8 reserved_at_3f0[0x3]; u8 log_max_current_mc_list[0x5]; - u8 reserved_at_3f8[0x3]; + u8 reserved_at_3f8[0x1]; + u8 silent_mode_query[0x1]; + u8 reserved_at_3fa[0x1]; u8 log_max_current_uc_list[0x5]; u8 general_obj_types[0x40]; @@ -2279,6 +2282,7 @@ enum mlx5_ifc_flow_destination_type { MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, + MLX5_IFC_FLOW_DESTINATION_TYPE_VHCA_RX = 0x4, MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, @@ -6265,7 +6269,9 @@ struct mlx5_ifc_query_l2_table_entry_out_bits { u8 reserved_at_40[0xa0]; - u8 reserved_at_e0[0x13]; + u8 reserved_at_e0[0x11]; + u8 silent_mode[0x1]; + u8 reserved_at_f2[0x1]; u8 vlan_valid[0x1]; u8 vlan[0xc]; @@ -6281,7 +6287,10 @@ struct mlx5_ifc_query_l2_table_entry_in_bits { u8 reserved_at_20[0x10]; u8 op_mod[0x10]; - u8 reserved_at_40[0x60]; + u8 reserved_at_40[0x40]; + + u8 silent_mode_query[0x1]; + u8 reserved_at_81[0x1f]; u8 reserved_at_a0[0x8]; u8 table_index[0x18]; -- 2.44.0