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Mon, 9 Mar 2026 02:34:51 -0700 From: Tariq Toukan To: Leon Romanovsky , Jason Gunthorpe , "Saeed Mahameed" , Tariq Toukan CC: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , Mark Bloch , , , , Gal Pressman , Dragos Tatulea , Moshe Shemesh , Shay Drory , Alexei Lazar Subject: [PATCH mlx5-next V2 1/9] net/mlx5: Add IFC bits for shared headroom pool PBMC support Date: Mon, 9 Mar 2026 11:34:27 +0200 Message-ID: <20260309093435.1850724-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260309093435.1850724-1-tariqt@nvidia.com> References: <20260309093435.1850724-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6732:EE_|IA1PR12MB8264:EE_ X-MS-Office365-Filtering-Correlation-Id: 69f4fcf4-f9d6-4eac-5c57-08de7dbf28ad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: nq3NnyRFwnz3ExpvgRTUyWNAPkDGyZW/WoRQV02+gHSdCeETHPvkYpn83fTDDSNnjz7zofZsQyEbtmub1KCuTBOcI/4lLuVXeL3bBifIsxw4F94Zpc0BlBIld3fRl3K3ukwlHOI78moXERKpiD2G5SbE0p32G0wFZHlPtaugrRdboZM23JiTL/Gn1/M2GDv2AK53RorR+9Z75ONSTFY5RFAZQfIhG6XPVnE2zJ/ZHeLb8YziFbvlC3lrxhH+Z2c+vE57x6g2YsIaBeBiSoKRohoB82CvcQU4GmFZrSCJVrwdfMETSd/MgdpRlQA6VKrwQz7WpcYf01NOTltJ0S5Td/KMhZ/xTw6hsrnShCoVKoZJbDlIJzEna1oPpw+g0kut5IIlQMV154YRGuNz7CyJwi5ec8UfkBSIsBAHpr5/KJR8GhAs+OLbEX4yk+vxyHknaeVxNzDgMvNBYyiufsgQvocEL7BE2aY+ymZduvAcWCr+YrADtd9220rjefrA3ZrzeS4T9QgtYD0FU97s3fOk+KgvCMymSyIWp3sDnc2oK3Jc3v/o2TtK+jWueq/UUgOYqf2tdNxZAhSoIYyF636oxpRlJ8mGyp3WqwQAvHFYmiXnwPb1OS67BMdZnrW8PuYs9uPl3QNzGQyvWpy0vMlGEY6gmm2o1YlRtPDtAIBIpfaaFLc/wd9OFCauUlV7r5hSfhFSRmy2LI1UV17Lix6tTxYDKSzaqp3L51J9jRBn+sH0TIxVE3ES2ZMu2SRBBMvG7AOkERJhKTLIh0VrxwNRLQ== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ukAPJBX3ofwQCBglZgbYzZwc2fe3a1antSvwABSFhqqkWYzYfiUAX7o9RaHJvfaRaSC9GiwUBENQ6tpoUmSQ8dSXmvi1nnPCwjTTW5nl7fBD7blm4NdIJ4oPNbOsNM0+A/+h0rgUyIWZ4PMjg2Uz+ZN1IQwitk6+F/UuSPN1t2eqeupQZZqFRLZkDX/F0tzbU9jr+Cyy5PFU2YIDrXsdqZIuz+9icN+EsLlLG8OPxjsuRog1pOhRNXPQfQKOFY20ZYAdEGHM2SOwThiAAnrqYGaFvWjmhjy4i2Ilypvw7///gNm031IQBBsTptQuxvFRHUHvl/ITvx88NvRe0AxeSNPcugxewTLGpaOC8QEJMoAuqzLTg1PwrDesyWmIz4zL7X/q5lqFyf8kM8YuaBiJ3Gdpd3nwViKptQdtn5LPY6iHj2kcmXS3/Nt+e8zCRI1S X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2026 09:35:10.6946 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 69f4fcf4-f9d6-4eac-5c57-08de7dbf28ad X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6732.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8264 From: Alexei Lazar Add hardware interface definitions for shared headroom pool (SHP) in port buffer management: - shp_pbmc_pbsr_support: capability bit in PCAM enhanced features indicating device support for shared headroom pool in PBMC/PBSR. - shared_headroom_pool: buffer entry in PBMC register (pbmc_reg_bits) for the shared headroom pool configuration, reusing the bufferx layout; reduce trailing reserved region accordingly. Signed-off-by: Alexei Lazar Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index a3948b36820d..a76c54bf1927 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -10845,7 +10845,9 @@ struct mlx5_ifc_pcam_enhanced_features_bits { u8 fec_200G_per_lane_in_pplm[0x1]; u8 reserved_at_1e[0x2a]; u8 fec_100G_per_lane_in_pplm[0x1]; - u8 reserved_at_49[0xa]; + u8 reserved_at_49[0x2]; + u8 shp_pbmc_pbsr_support[0x1]; + u8 reserved_at_4c[0x7]; u8 buffer_ownership[0x1]; u8 resereved_at_54[0x14]; u8 fec_50G_per_lane_in_pplm[0x1]; @@ -12090,8 +12092,9 @@ struct mlx5_ifc_pbmc_reg_bits { u8 port_buffer_size[0x10]; struct mlx5_ifc_bufferx_reg_bits buffer[10]; + struct mlx5_ifc_bufferx_reg_bits shared_headroom_pool; - u8 reserved_at_2e0[0x80]; + u8 reserved_at_320[0x40]; }; struct mlx5_ifc_sbpr_reg_bits { -- 2.44.0