From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 311933B3C02; Mon, 9 Mar 2026 12:05:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773057935; cv=none; b=NgrNy5lUstgKpye505MXjp+p6aub5hVHHQnjJWjajfvs8/v1qoMLLUPC+td3elAu0hS6GHOv3bZ6oHY/PwCB2NZ0H5uRFS6UQ/GrrSaqDTwBv7MBgesuVSdbSruPVrzDU/QXaVFHEgH914dV1Iwox4kFKIdOu25IviWOwbhCqps= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773057935; c=relaxed/simple; bh=6Pumgs9aKvTbPRWiTgq6PeLMTuhaF5ZPLEmtoaBUO8k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EsTbJ2cvmQp3SdWJte+XEIzU7OltTSld2YMyyATlVNe6Dvxrp6okyZlof2XNlXSrfPoBLGqbsNuFnW467nn/HZNMsCr/cfuln18ljEyYKh1Yb1ZUWB7Z5fdF9541ekzNJEFb0GE6vZI3Bza8ghrhBdGev5lvDF4SgQOgLLh4K38= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=PneR0djy; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="PneR0djy" X-UUID: 3dd64b1e1bb011f1a39cd589f645bc18-20260309 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=FRI44TdrdZ3Legx0P7loaEhsz45HIny8Im0Ko5rp3s8=; b=PneR0djy53DBUyiMFQDOf+8gWHHU1lQQmsvDcGsXKWcS8KlEhXFP/RnaVWxcmLQ9qXZ1pZVLHWfPA0IXd03XJf7KpOo5NiW5tCZMbdCJDHFHUyR+5XPU1pFPodSpHj7zrX1Ka/rzGKj5DYGWH+6bx/oTX/EurvtPxf7EGgE7sn4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.11,REQID:da60a2ea-a7fe-46d1-99a8-d090398c5f3f,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:89c9d04,CLOUDID:6e1f6ff1-16bd-4243-b4ca-b08ca08ab1d8,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 3dd64b1e1bb011f1a39cd589f645bc18-20260309 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 514206857; Mon, 09 Mar 2026 20:05:19 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Mon, 9 Mar 2026 20:05:17 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Mon, 9 Mar 2026 20:05:17 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Richard Cochran , Bartosz Golaszewski , Chen-Yu Tsai , Miles Chen CC: , , , , , , , Qiqi Wang , , , , Subject: [PATCH v6 02/18] clk: mediatek: clk-mux: Make sure bypass clk enabled while setting MFG rate Date: Mon, 9 Mar 2026 20:04:44 +0800 Message-ID: <20260309120512.3624804-3-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260309120512.3624804-1-irving-ch.lin@mediatek.com> References: <20260309120512.3624804-1-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Irving-CH Lin Enable bypass clock before MFG changing rate, to make sure MFG reference clock available during transient. Fixes: b66add7a74e8 ("clk: mediatek: mux: add clk notifier functions") Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/clk-mux.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index 5f4b07e7c757..574e35a42115 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -414,16 +414,21 @@ static int mtk_clk_mux_notifier_cb(struct notifier_block *nb, struct clk_notifier_data *data = _data; struct clk_hw *hw = __clk_get_hw(data->clk); struct mtk_mux_nb *mux_nb = to_mtk_mux_nb(nb); + struct clk_hw *p_hw = clk_hw_get_parent_by_index(hw, mux_nb->bypass_index); int ret = 0; switch (event) { case PRE_RATE_CHANGE: - mux_nb->original_index = mux_nb->ops->get_parent(hw); - ret = mux_nb->ops->set_parent(hw, mux_nb->bypass_index); + ret = clk_prepare_enable(p_hw->clk); + if (ret == 0) { + mux_nb->original_index = mux_nb->ops->get_parent(hw); + ret = mux_nb->ops->set_parent(hw, mux_nb->bypass_index); + } break; case POST_RATE_CHANGE: case ABORT_RATE_CHANGE: ret = mux_nb->ops->set_parent(hw, mux_nb->original_index); + clk_disable_unprepare(p_hw->clk); break; } -- 2.45.2